关键词：rk312x-pinctrl.dtsi ,linux_3.10,rockchip,dts
dts — rk312x-pinctrl.dtsi
// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
#include <dt-bindings/interrupt-controller/arm-gic.h>
#include <dt-bindings/gpio/gpio.h>
#include <dt-bindings/pinctrl/rockchip.h>
#include <dt-bindings/pinctrl/rockchip-rk312x.h>
/ {
pinctrl: pinctrl@20008000 {
compatible = "rockchip,rk312x-pinctrl";
reg = <0x20008000 0xA8>,
<0x200080A8 0x4C>,
<0x20008118 0x20>,
<0x20008100 0x04>;
reg-names = "base", "mux", "pull", "drv";
#address-cells = <1>;
#size-cells = <1>;
ranges;
gpio0: gpio0@2007c000 {
compatible = "rockchip,gpio-bank";
reg = <0x2007c000 0x100>;
interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&clk_gates8 9>;
gpio-controller;
#gpio-cells = <2>;
interrupt-controller;
#interrupt-cells = <2>;
};
gpio1: gpio1@20080000 {
compatible = "rockchip,gpio-bank";
reg = <0x20080000 0x100>;
interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&clk_gates8 10>;
gpio-controller;
#gpio-cells = <2>;
interrupt-controller;
#interrupt-cells = <2>;
};
gpio2: gpio2@20084000 {
compatible = "rockchip,gpio-bank";
reg = <0x20084000 0x100>;
interrupts = <GIC_SPI 38 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&clk_gates8 11>;
gpio-controller;
#gpio-cells = <2>;
interrupt-controller;
#interrupt-cells = <2>;
};
gpio3: gpio3@20088000 {
compatible = "rockchip,gpio-bank";
reg = <0x20088000 0x100>;
interrupts = <GIC_SPI 39 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&clk_gates8 12>;
gpio-controller;
#gpio-cells = <2>;
interrupt-controller;
#interrupt-cells = <2>;
};
gpio15: gpio15@2008A000 {
compatible = "rockchip,gpio-bank";
reg = <0x20086000 0x100>;
interrupts = <GIC_SPI 127 IRQ_TYPE_LEVEL_HIGH>;//127 = 160-32-1
clocks = <&clk_gates8 12>;
gpio-controller;
#gpio-cells = <2>;
interrupt-controller;
#interrupt-cells = <2>;
};
pcfg_pull_up: pcfg_pull_up {
bias-pull-up;
};
pcfg_pull_down: pcfg_pull_down {
bias-pull-down;
};
pcfg_pull_none: pcfg_pull_none {
bias-disable;
};
gpio0_uart0 {
uart0_xfer: uart0-xfer {
rockchip,pins = <UART0_SIN>,
<UART0_SOUT>;
rockchip,pull = <VALUE_PULL_UPDOWN_DISABLE>;
};
uart0_cts: uart0-cts {
rockchip,pins = <UART0_CTSN>;
rockchip,pull = <VALUE_PULL_DEFAULT>;
};
uart0_rts: uart0-rts {
rockchip,pins = <UART0_RTSN>;
rockchip,pull = <VALUE_PULL_DEFAULT>;
};
uart0_rts_gpio: uart0-rts-gpio {
rockchip,pins = <FUNC_TO_GPIO(UART0_RTSN)>;
rockchip,pull = <VALUE_PULL_DEFAULT>;
};
};
gpio1_uart1 {
uart1_xfer: uart1-xfer {
rockchip,pins = <UART1_SIN>,
<UART1_SOUT>;
rockchip,pull = <VALUE_PULL_DEFAULT>;
};
uart1_cts: uart1-cts {
rockchip,pins = <UART1_CTSN>;
rockchip,pull = <VALUE_PULL_DEFAULT>;
};
uart1_rts: uart1-rts {
rockchip,pins = <UART1_RTSN>;
rockchip,pull = <VALUE_PULL_DEFAULT>;
};
uart1_rts_gpio: uart1-rts-gpio {
rockchip,pins = <FUNC_TO_GPIO(UART1_RTSN)>;
rockchip,pull = <VALUE_PULL_DEFAULT>;
};
};
gpio1_uart2 {
uart2_xfer: uart2-xfer {
rockchip,pins = <UART2_SIN>,
<UART2_SOUT>;
rockchip,pull = <VALUE_PULL_DEFAULT>;
};
uart2_cts: uart2-cts {
rockchip,pins = <UART2_CTSN>;
rockchip,pull = <VALUE_PULL_DEFAULT>;
};
uart2_rts: uart2-rts {
rockchip,pins = <UART2_RTSN>;
rockchip,pull = <VALUE_PULL_DEFAULT>;
};
uart2_rts_gpio: uart2-rts-gpio {
rockchip,pins = <FUNC_TO_GPIO(UART2_RTSN)>;
rockchip,pull = <VALUE_PULL_DEFAULT>;
};
};
gpio0_i2c0 {
i2c0_sda:i2c0-sda {
rockchip,pins = <I2C0_SDA>;
rockchip,pull = <VALUE_PULL_DEFAULT>;
};
i2c0_scl:i2c0-scl {
rockchip,pins = <I2C0_SCL>;
rockchip,pull = <VALUE_PULL_DEFAULT>;
};
i2c0_gpio: i2c0-gpio {
rockchip,pins = <FUNC_TO_GPIO(I2C0_SDA)>, <FUNC_TO_GPIO(I2C0_SCL)>;
rockchip,pull = <VALUE_PULL_DEFAULT>;
};
};
gpio0_i2c1 {
i2c1_sda:i2c1-sda {
rockchip,pins = <I2C1_SDA>;
rockchip,pull = <VALUE_PULL_DEFAULT>;
};
i2c1_scl:i2c1-scl {
rockchip,pins = <I2C1_SCL>;
rockchip,pull = <VALUE_PULL_DEFAULT>;
};
i2c1_gpio: i2c1-gpio {
rockchip,pins = <FUNC_TO_GPIO(I2C1_SDA)>, <FUNC_TO_GPIO(I2C1_SCL)>;
rockchip,pull = <VALUE_PULL_DEFAULT>;
};
};
gpio1_i2c2 {
i2c2_sda:i2c2-sda {
rockchip,pins = <I2C2_SDA>;
rockchip,pull = <VALUE_PULL_DEFAULT>;
};
i2c2_scl:i2c2-scl {
rockchip,pins = <I2C2_SCL>;
rockchip,pull = <VALUE_PULL_DEFAULT>;
};
i2c2_gpio: i2c2-gpio {
rockchip,pins = <FUNC_TO_GPIO(I2C2_SDA)>, <FUNC_TO_GPIO(I2C2_SCL)>;
rockchip,pull = <VALUE_PULL_DEFAULT>;
};
};
gpio0_i2c3 {
i2c3_sda:i2c3-sda {
rockchip,pins = <I2C3_SDA>;
rockchip,pull = <VALUE_PULL_DEFAULT>;
};
i2c3_scl:i2c3-scl {
rockchip,pins = <I2C3_SCL>;
rockchip,pull = <VALUE_PULL_DEFAULT>;
};
i2c3_gpio: i2c3-gpio {
rockchip,pins = <FUNC_TO_GPIO(I2C3_SDA)>, <FUNC_TO_GPIO(I2C3_SCL)>;
rockchip,pull = <VALUE_PULL_DEFAULT>;
};
};
gpio1_spi0 {
spi0_txd_mux0:spi0-txd-mux0 {
rockchip,pins = <SPI0_TXD_MUX0>;
rockchip,pull = <VALUE_PULL_DEFAULT>;
};
spi0_rxd_mux0:spi0-rxd-mux0 {
rockchip,pins = <SPI0_RXD_MUX0>;
rockchip,pull = <VALUE_PULL_DEFAULT>;
};
spi0_clk_mux0:spi0-clk-mux0 {
rockchip,pins = <SPI0_CLK_MUX0>;
rockchip,pull = <VALUE_PULL_DEFAULT>;
};
spi0_cs0_mux0:spi0-cs0-mux0 {
rockchip,pins = <SPI0_CS0_MUX0>;
rockchip,pull = <VALUE_PULL_DEFAULT>;
};
spi0_cs1_mux0:spi0-cs1-mux0 {
rockchip,pins = <SPI0_CS1_MUX0>;
rockchip,pull = <VALUE_PULL_DEFAULT>;
};
spi0_txd_mux1:spi0-txd-mux1 {
rockchip,pins = <SPI0_TXD_MUX1>;
rockchip,pull = <VALUE_PULL_DEFAULT>;
};
spi0_rxd_mux1:spi0-rxd-mux1 {
rockchip,pins = <SPI0_RXD_MUX1>;
rockchip,pull = <VALUE_PULL_DEFAULT>;
};
spi0_clk_mux1:spi0-clk-mux1 {
rockchip,pins = <SPI0_CLK_MUX1>;
rockchip,pull = <VALUE_PULL_DEFAULT>;
};
spi0_cs0_mux1:spi0-cs0-mux1 {
rockchip,pins = <SPI0_CS0_MUX1>;
rockchip,pull = <VALUE_PULL_DEFAULT>;
};
spi0_cs1_mux1:spi0-cs1-mux1 {
rockchip,pins = <SPI0_CS1_MUX1>;
rockchip,pull = <VALUE_PULL_DEFAULT>;
};
spi0_txd_mux2:spi0-txd-mux2 {
rockchip,pins = <SPI0_TXD_MUX2>;
rockchip,pull = <VALUE_PULL_DEFAULT>;
};
spi0_rxd_mux2:spi0-rxd-mux2 {
rockchip,pins = <SPI0_RXD_MUX2>;
rockchip,pull = <VALUE_PULL_DEFAULT>;
};
spi0_clk_mux2:spi0-clk-mux2 {
rockchip,pins = <SPI0_CLK_MUX2>;
rockchip,pull = <VALUE_PULL_DEFAULT>;
};
spi0_cs0_mux2:spi0-cs0-mux2 {
rockchip,pins = <SPI0_CS0_MUX2>;
rockchip,pull = <VALUE_PULL_DEFAULT>;
};
};
gpio1_hdmi {
hdmi_cec:hdmi-cec {
rockchip,pins = <HDMI_CEC>;
rockchip,pull = <VALUE_PULL_DEFAULT>;
//rockchip,drive = <VALUE_DRV_DEFAULT>;
};
hdmi_sda:hdmi-sda {
rockchip,pins = <HDMI_DSDA>;
rockchip,pull = <VALUE_PULL_DEFAULT>;
//rockchip,drive = <VALUE_DRV_DEFAULT>;
};
hdmi_scl:hdmi-scl {
rockchip,pins = <HDMI_DSCL>;
rockchip,pull = <VALUE_PULL_DEFAULT>;
//rockchip,drive = <VALUE_DRV_DEFAULT>;
};
hdmi_hpd:hdmi-hpd {
rockchip,pins = <HDMI_HPD>;
rockchip,pull = <VALUE_PULL_DEFAULT>;
//rockchip,drive = <VALUE_DRV_DEFAULT>;
};
hdmi_gpio: hdmi-gpio {
rockchip,pins = <FUNC_TO_GPIO(HDMI_CEC)>, <FUNC_TO_GPIO(HDMI_DSDA)>, <FUNC_TO_GPIO(HDMI_DSCL)>, <FUNC_TO_GPIO(HDMI_HPD)>;
rockchip,pull = <VALUE_PULL_DEFAULT>;
//rockchip,drive = <VALUE_DRV_DEFAULT>;
};
};
gpio1_i2s0 {
i2s0_mclk_mux0:i2s0-mclk-mux0 {
rockchip,pins = <I2S0_MCLK_MUX0>;
rockchip,pull = <VALUE_PULL_DEFAULT>;
};
i2s0_sclk_mux0:i2s0-sclk-mux0 {
rockchip,pins = <I2S0_SCLK_MUX0>;
rockchip,pull = <VALUE_PULL_DEFAULT>;
};
i2s0_lrckrx_mux0:i2s0-lrckrx-mux0 {
rockchip,pins = <I2S0_LRCKRX_MUX0>;
rockchip,pull = <VALUE_PULL_DEFAULT>;
};
i2s0_lrcktx_mux0:i2s0-lrcktx-mux0 {
rockchip,pins = <I2S0_LRCKTX_MUX0>;
rockchip,pull = <VALUE_PULL_DEFAULT>;
};
i2s0_sdo_mux0:i2s0-sdo-mux0 {
rockchip,pins = <I2S0_SDO_MUX0>;
rockchip,pull = <VALUE_PULL_DEFAULT>;
};
i2s0_sdi_mux0:i2s0-sdi-mux0 {
rockchip,pins = <I2S0_SDI_MUX0>;
rockchip,pull = <VALUE_PULL_DEFAULT>;
};
i2s0_gpio_mux0: i2s0-gpio-mux0 {
rockchip,pins = <FUNC_TO_GPIO(I2S0_MCLK_MUX0)>,
<FUNC_TO_GPIO(I2S0_SCLK_MUX0)>,
<FUNC_TO_GPIO(I2S0_LRCKRX_MUX0)>,
<FUNC_TO_GPIO(I2S0_LRCKTX_MUX0)>,
<FUNC_TO_GPIO(I2S0_SDO_MUX0)>,
<FUNC_TO_GPIO(I2S0_SDI_MUX0)>;
rockchip,pull = <VALUE_PULL_DEFAULT>;
};
i2s0_mclk_mux1:i2s0-mclk-mux1 {
rockchip,pins = <I2S0_MCLK_MUX1>;
rockchip,pull = <VALUE_PULL_DEFAULT>;
};
i2s0_sclk_mux1:i2s0-sclk-mux1 {
rockchip,pins = <I2S0_SCLK_MUX1>;
rockchip,pull = <VALUE_PULL_DEFAULT>;
};
i2s0_lrckrx_mux1:i2s0-lrckrx-mux1 {
rockchip,pins = <I2S0_LRCKRX_MUX1>;
rockchip,pull = <VALUE_PULL_DEFAULT>;
};
i2s0_lrcktx_mux1:i2s0-lrcktx-mux1 {
rockchip,pins = <I2S0_LRCKTX_MUX1>;
rockchip,pull = <VALUE_PULL_DEFAULT>;
};
i2s0_sdo_mux1:i2s0-sdo-mux1 {
rockchip,pins = <I2S0_SDO_MUX1>;
rockchip,pull = <VALUE_PULL_DEFAULT>;
};
i2s0_sdi_mux1:i2s0-sdi-mux1 {
rockchip,pins = <I2S0_SDI_MUX1>;
rockchip,pull = <VALUE_PULL_DEFAULT>;
};
i2s0_gpio_mux1: i2s0-gpio-mux1 {
rockchip,pins = <FUNC_TO_GPIO(I2S0_MCLK_MUX1)>,
<FUNC_TO_GPIO(I2S0_SCLK_MUX1)>,
<FUNC_TO_GPIO(I2S0_LRCKRX_MUX1)>,
<FUNC_TO_GPIO(I2S0_LRCKTX_MUX1)>,
<FUNC_TO_GPIO(I2S0_SDO_MUX1)>,
<FUNC_TO_GPIO(I2S0_SDI_MUX1)>;
rockchip,pull = <VALUE_PULL_DEFAULT>;
};
};
gpio0_spdif {
spdif_tx: spdif-tx {
rockchip,pins = <SPDIF_TX>;
rockchip,pull = <VALUE_PULL_DEFAULT>;
};
};
gpio0_emmc0 {
emmc0_clk: emmc0-clk {
rockchip,pins = <EMMC_CLKOUT>;
rockchip,pull = <VALUE_PULL_DEFAULT>;
};
emmc0_cmd_mux0: emmc0-cmd-mux0 {
rockchip,pins = <EMMC_CMD_MUX0>;
rockchip,pull = <VALUE_PULL_UP>;
};
emmc0_cmd_mux1: emmc0-cmd-mux1 {
rockchip,pins = <EMMC_CMD_MUX1>;
rockchip,pull = <VALUE_PULL_UP>;
};
emmc0_bus1: emmc0-bus-width1 {
rockchip,pins = <EMMC_D0>;
rockchip,pull = <VALUE_PULL_UP>;
};
emmc0_bus4: emmc0-bus-width4 {
rockchip,pins = <EMMC_D0>,
<EMMC_D1>,
<EMMC_D2 >,
<EMMC_D3>;
rockchip,pull = <VALUE_PULL_UP>;
};
};
gpio1_sdmmc0 {
sdmmc0_clk: sdmmc0-clk {
rockchip,pins = <MMC0_CLKOUT>;
rockchip,pull = <VALUE_PULL_DEFAULT>;
};
sdmmc0_cmd: sdmmc0-cmd {
rockchip,pins = <MMC0_CMD>;
rockchip,pull = <VALUE_PULL_UP>;
};
sdmmc0_dectn: sdmmc0-dectn{
rockchip,pins = <MMC0_DETN>;
rockchip,pull = <VALUE_PULL_UP>;
};
sdmmc0_pwren: sdmmc0-pwren{
rockchip,pins = <MMC0_PWREN>;
rockchip,pull = <VALUE_PULL_UP>;
};
sdmmc0_bus1: sdmmc0-bus-width1 {
rockchip,pins = <MMC0_D0>;
rockchip,pull = <VALUE_PULL_UP>;
};
sdmmc0_bus4: sdmmc0-bus-width4 {
rockchip,pins = <MMC0_D0>,
<MMC0_D1>,
<MMC0_D2>,
<MMC0_D3>;
rockchip,pull = <VALUE_PULL_UP>;
};
sdmmc0_gpio: sdmmc0_gpio{
rockchip,pins =
<GPIO1_B7>, //CMD
<GPIO1_C0>, //CLK
<GPIO1_C1>, //DET
<GPIO1_B6>, //PWREN
<GPIO1_C2>, //D0
<GPIO1_C3>, //D1
<GPIO1_C4>, //D2
<GPIO1_C5>; //D3
rockchip,pull = <VALUE_PULL_UP>;
};
};
gpio2_nandc {
nandc_ale:nandc-ale {
rockchip,pins = <NAND_ALE>;
rockchip,pull = <VALUE_PULL_DEFAULT>;
};
nandc_cle:nandc-cle {
rockchip,pins = <NAND_CLE>;
rockchip,pull = <VALUE_PULL_DEFAULT>;
};
nandc_wrn:nandc-wrn {
rockchip,pins = <NAND_WRN>;
rockchip,pull = <VALUE_PULL_DEFAULT>;
};
nandc_rdn:nandc-rdn {
rockchip,pins = <NAND_RDN>;
rockchip,pull = <VALUE_PULL_DEFAULT>;
};
nandc_rdy:nandc-rdy {
rockchip,pins = <NAND_RDY>;
rockchip,pull = <VALUE_PULL_DEFAULT>;
};
nandc_cs0:nandc-cs0 {
rockchip,pins = <NAND_CS0>;
rockchip,pull = <VALUE_PULL_DEFAULT>;
};
nandc_data: nandc-data {
rockchip,pins = <NAND_D0>,
<NAND_D1>,
<NAND_D2>,
<NAND_D3>,
<NAND_D4>,
<NAND_D5>,
<NAND_D6>,
<NAND_D7>;
rockchip,pull = <VALUE_PULL_DEFAULT>;
};
};
gpio0_sdio0 {
sdio0_pwren: sdio0_pwren {
rockchip,pins = <MMC1_PWREN>;
rockchip,pull = <VALUE_PULL_DEFAULT>;
};
sdio0_cmd: sdio0_cmd {
rockchip,pins = <MMC1_CMD>;
rockchip,pull = <VALUE_PULL_UPDOWN_DISABLE>;
};
sdio0_clk: sdio0_clk {
rockchip,pins = <SDMMC_CLKOUT>;
rockchip,pull = <VALUE_PULL_UPDOWN_DISABLE>;
};
sdio0_bus1: sdio0-bus-width1 {
rockchip,pins = <SDMMC_DATA0>;
rockchip,pull = <VALUE_PULL_UPDOWN_DISABLE>;
};
sdio0_bus4: sdio0-bus-width4 {
rockchip,pins = <SDMMC_DATA0>,
<SDMMC_DATA1>,
<SDMMC_DATA2>,
<SDMMC_DATA3>;
rockchip,pull = <VALUE_PULL_UPDOWN_DISABLE>;
};
sdio0_gpio: sdio0_gpio{
rockchip,pins = <GPIO0_D6>, //pwren
<GPIO0_A3>, //cmd
<GPIO1_A0>, //clk
<GPIO1_A1>, //data0
<GPIO1_A2>, //data1
<GPIO1_A4>, //data2
<GPIO1_A5>; //data3
rockchip,pull = <VALUE_PULL_UPDOWN_DISABLE>;
};
};
gpio0_pwm{
pwm0_pin:pwm0 {
rockchip,pins = <PWM0>;
rockchip,pull = <VALUE_PULL_DEFAULT>;
};
pwm1_pin:pwm1 {
rockchip,pins = <PWM1>;
rockchip,pull = <VALUE_PULL_DEFAULT>;
};
pwm2_pin:pwm2 {
rockchip,pins = <PWM2>;
rockchip,pull = <VALUE_PULL_DEFAULT>;
};
pwm3_pin:pwm3 {
rockchip,pins = <PWM_IRIN>;
rockchip,pull = <VALUE_PULL_DEFAULT>;
};
};
gpio2_gmac {
gmac_rxdv:gmac-rxdv {
rockchip,pins = <GMAC_RXDV>;
rockchip,pull = <VALUE_PULL_DEFAULT>;
};
gmac_txclk:gmac-txclk {
rockchip,pins = <GMAC_TXCLK>;
rockchip,pull = <VALUE_PULL_DEFAULT>;
};
gmac_crs:gmac-crs {
rockchip,pins = <GMAC_CRS>;
rockchip,pull = <VALUE_PULL_DEFAULT>;
};
gmac_rxclk:gmac-rxclk {
rockchip,pins = <GMAC_RXCLK>;
rockchip,pull = <VALUE_PULL_DEFAULT>;
};
gmac_mdio:gmac-mdio {
rockchip,pins = <GMAC_MDIO>;
rockchip,pull = <VALUE_PULL_DEFAULT>;
};
gmac_txen:gmac-txen {
rockchip,pins = <GMAC_TXEN>;
rockchip,pull = <VALUE_PULL_DEFAULT>;
};
gmac_clk:gmac-clk {
rockchip,pins = <GMAC_CLK>;
rockchip,pull = <VALUE_PULL_DEFAULT>;
};
gmac_rxer:gmac-rxer {
rockchip,pins = <GMAC_RXER>;
rockchip,pull = <VALUE_PULL_DEFAULT>;
};
gmac_rxd1:gmac-rxd1 {
rockchip,pins = <GMAC_RXD1>;
rockchip,pull = <VALUE_PULL_DEFAULT>;
};
gmac_rxd0:gmac-rxd0 {
rockchip,pins = <GMAC_RXD0>;
rockchip,pull = <VALUE_PULL_DEFAULT>;
};
gmac_txd1:gmac-txd1 {
rockchip,pins = <GMAC_TXD1>;
rockchip,pull = <VALUE_PULL_DEFAULT>;
};
gmac_txd0:gmac-txd0 {
rockchip,pins = <GMAC_TXD0>;
rockchip,pull = <VALUE_PULL_DEFAULT>;
};
gmac_rxd3:gmac-rxd3 {
rockchip,pins = <GMAC_RXD3>;
rockchip,pull = <VALUE_PULL_DEFAULT>;
};
gmac_rxd2:gmac-rxd2 {
rockchip,pins = <GMAC_RXD2>;
rockchip,pull = <VALUE_PULL_DEFAULT>;
};
gmac_txd2:gmac-txd2 {
rockchip,pins = <GMAC_TXD2>;
rockchip,pull = <VALUE_PULL_DEFAULT>;
};
gmac_txd3:gmac-txd3 {
rockchip,pins = <GMAC_TXD3>;
rockchip,pull = <VALUE_PULL_DEFAULT>;
};
gmac_col:gmac-col {
rockchip,pins = <GMAC_COL>;
rockchip,pull = <VALUE_PULL_DEFAULT>;
};
gmac_col_gpio:gmac-col-gpio {
rockchip,pins = <GPIO2_D0>;
rockchip,pull = <VALUE_PULL_DEFAULT>;
};
gmac_mdc:gmac-mdc {
rockchip,pins = <GMAC_MDC>;
rockchip,pull = <VALUE_PULL_DEFAULT>;
};
};
gpio2_lcdc0 {
lcdc0_lcdc:lcdc0-lcdc {
rockchip,pins =
<LCDC0_DCLK>,
<LCDC0_DEN>,
<LCDC0_HSYNC>,
<LCDC0_VSYNC>;
rockchip,pull = <VALUE_PULL_DISABLE>;
};
lcdc0_gpio:lcdc0-gpio {
rockchip,pins =
<FUNC_TO_GPIO(LCDC0_DCLK)>,
<FUNC_TO_GPIO(LCDC0_DEN)>,
<FUNC_TO_GPIO(LCDC0_HSYNC)>,
<FUNC_TO_GPIO(LCDC0_VSYNC)>;
rockchip,pull = <VALUE_PULL_DISABLE>;
};
};
gpio2_lcdc0_d {
lcdc0_lcdc_d: lcdc0-lcdc_d {
rockchip,pins =
<LCDC0_D10>,
<LCDC0_D11>,
<LCDC0_D12>,
<LCDC0_D13>,
<LCDC0_D14>,
<LCDC0_D15>,
<LCDC0_D16>,
<LCDC0_D17>;
/*
<LCDC0_D18>,
<LCDC0_D19>,
<LCDC0_D20>,
<LCDC0_D21>,
<LCDC0_D22>,
<LCDC0_D23>;
*/
rockchip,pull = <VALUE_PULL_DISABLE>;
};
lcdc0_lcdc_gpio: lcdc0-lcdc_gpio {
rockchip,pins =
<FUNC_TO_GPIO(LCDC0_D10)>,
<FUNC_TO_GPIO(LCDC0_D11)>,
<FUNC_TO_GPIO(LCDC0_D12)>,
<FUNC_TO_GPIO(LCDC0_D13)>,
<FUNC_TO_GPIO(LCDC0_D14)>,
<FUNC_TO_GPIO(LCDC0_D15)>,
<FUNC_TO_GPIO(LCDC0_D16)>,
<FUNC_TO_GPIO(LCDC0_D17)>;
/*
<FUNC_TO_GPIO(LCDC0_D18)>,
<FUNC_TO_GPIO(LCDC0_D19)>,
<FUNC_TO_GPIO(LCDC0_D20)>,
<FUNC_TO_GPIO(LCDC0_D21)>,
<FUNC_TO_GPIO(LCDC0_D22)>,
<FUNC_TO_GPIO(LCDC0_D23)>;
*/
rockchip,pull = <VALUE_PULL_DOWN>;
};
};
//to add
};
};