关键词：rk3288-firefly-beta.dts ,linux_3.10,rockchip,dts
dts — rk3288-firefly-beta.dts
/dts-v1/; #include "rk3288-firefly.dtsi" / { model = "Firefly-RK3288 Beta"; compatible = "firefly,firefly-rk3288-beta", "rockchip,rk3288"; }; &ir { gpios = <&gpio7 5 GPIO_ACTIVE_LOW>; }; &pinctrl { act8846 { pmic_vsel: pmic-vsel { rockchip,pins = <7 1 RK_FUNC_GPIO &pcfg_output_low>; }; }; ir { ir_int: ir-int { rockchip,pins = <7 5 RK_FUNC_GPIO &pcfg_pull_up>; }; }; }; &pwm0 { status = "okay"; }; TIVE_HIGH>; BT,reset_gpio = <&gpio4 GPIO_D5 GPIO_ACTIVE_HIGH>; BT,wake_gpio = <&gpio4 GPIO_D2 GPIO_ACTIVE_HIGH>; BT,wake_host_irq = <&gpio4 GPIO_D7 GPIO_ACTIVE_LOW>; status = "okay"; };*/ usb_control { compatible = "rockchip,rk3036-usb-control"; host_drv_gpio = <&gpio2 GPIO_C7 GPIO_ACTIVE_LOW>; otg_drv_gpio = <&gpio0 GPIO_D2 GPIO_ACTIVE_LOW>; rockchip,remote_wakeup; rockchip,usb_irq_wakeup; }; key { compatible = "rockchip,key"; }; codec_hdmi_spdif: codec-hdmi-spdif { compatible = "hdmi-spdif"; }; rockchip-hdmi-spdif { compatible = "rockchip-hdmi-spdif"; dais { dai0 { audio-codec = <&codec_hdmi_spdif>; audio-controller = <&spdif>; }; }; }; rockchip-spdif-card { compatible = "rockchip-spdif-card"; dais { dai0 { audio-codec = <&codec_hdmi_spdif>; audio-controller = <&spdif>; }; }; }; rockchip-audio { compatible = "rk3036-audio"; dais { dai0 { audio-codec = <&codec>; audio-controller = <&i2s>; format = "i2s"; //continuous-clock; //bitclock-inversion; //frame-inversion; //bitclock-master; //frame-master; }; }; }; }; &uart0{ status = "okay"; dma-names = "!tx", "!rx"; pinctrl-0 = <&uart0_xfer &uart0_cts>; }; &nandc { status = "okay"; // used nand set "okay" ,used emmc set "disabled" }; &nandc0reg { status = "disabled"; // used nand set "disabled" ,used emmc set "okay" }; &emmc { clock-frequency = <37500000>; clock-freq-min-max = <400000 37500000>; supports-highspeed; supports-emmc; bootpart-no-access; supports-DDR_MODE; ignore-pm-notify; keep-power-in-suspend; //poll-hw-reset status = "disabled"; }; &sdmmc { clock-frequency = <37500000>; clock-freq-min-max = <400000 37500000>; supports-highspeed; supports-sd; broken-cd; card-detect-delay = <200>; ignore-pm-notify; keep-power-in-suspend; //vmmc-supply = <&rk808_ldo5_reg>; status = "okay"; }; &sdio { clock-frequency = <37500000>; clock-freq-min-max = <200000 37500000>; supports-highspeed; supports-sdio; ignore-pm-notify; keep-power-in-suspend; cap-sdio-irq; status = "okay"; }; &i2c1 { status = "okay"; rtc@51 { compatible = "rtc,hym8563"; reg = <0x51>; //irq_gpio = <&gpio0 GPIO_A4 IRQ_TYPE_EDGE_FALLING>; }; }; &rk_screen { display-timings = <&disp_timings>; }; &fb { rockchip,disp-mode = <NO_DUAL>; rockchip,uboot-logo-on = <1>; }; &lcdc { status = "okay"; }; &tve { status = "okay"; }; &hdmi { status = "okay"; //rockchips,hdmi_audio_source = <0>; }; &vmac { // pmu_regulator = "act_ldo5"; // pmu_enable_level = <1>; //1->HIGH, 0->LOW // power-gpio = <&gpio0 GPIO_A6 GPIO_ACTIVE_HIGH>; reset-gpio = <&gpio2 GPIO_C6 GPIO_ACTIVE_LOW>; }; &dwc_control_usb { usb_uart { status = "disabled"; }; }; &pwm2 { status = "okay"; }; &remotectl { handle_cpu_id = <1>; ir_key1{ rockchip,usercode = <0x4040>; rockchip,key_table = <0xf2 KEY_REPLY>, <0xba KEY_BACK>, <0xf4 KEY_UP>, <0xf1 KEY_DOWN>, <0xef KEY_LEFT>, <0xee KEY_RIGHT>, <0xbd KEY_HOME>, <0xea KEY_VOLUMEUP>, <0xe3 KEY_VOLUMEDOWN>, <0xe2 KEY_SEARCH>, <0xb2 KEY_POWER>, <0xbc KEY_MUTE>, <0xec KEY_MENU>, <0xbf 0x190>, <0xe0 0x191>, <0xe1 0x192>, <0xe9 183>, <0xe6 248>, <0xe8 185>, <0xe7 186>, <0xf0 388>, <0xbe 0x175>; }; ir_key2{ rockchip,usercode = <0xff00>; rockchip,key_table = <0xf9 KEY_HOME>, <0xbf KEY_BACK>, <0xfb KEY_MENU>, <0xaa KEY_REPLY>, <0xb9 KEY_UP>, <0xe9 KEY_DOWN>, <0xb8 KEY_LEFT>, <0xea KEY_RIGHT>, <0xeb KEY_VOLUMEDOWN>, <0xef KEY_VOLUMEUP>, <0xf7 KEY_MUTE>, <0xe7 KEY_POWER>, <0xfc KEY_POWER>, <0xa9 KEY_VOLUMEDOWN>, <0xa8 KEY_VOLUMEDOWN>, <0xe0 KEY_VOLUMEDOWN>, <0xa5 KEY_VOLUMEDOWN>, <0xab 183>, <0xb7 388>, <0xf8 184>, <0xaf 185>, <0xed KEY_VOLUMEDOWN>, <0xee 186>, <0xb3 KEY_VOLUMEDOWN>, <0xf1 KEY_VOLUMEDOWN>, <0xf2 KEY_VOLUMEDOWN>, <0xf3 KEY_SEARCH>, <0xb4 KEY_VOLUMEDOWN>, <0xbe KEY_SEARCH>; }; ir_key3{ rockchip,usercode = <0x1dcc>; rockchip,key_table = <0xee KEY_REPLY>, <0xf0 KEY_BACK>, <0xf8 KEY_UP>, <0xbb KEY_DOWN>, <0xef KEY_LEFT>, <0xed KEY_RIGHT>, <0xfc KEY_HOME>, <0xf1 KEY_VOLUMEUP>, <0xfd KEY_VOLUMEDOWN>, <0xb7 KEY_SEARCH>, <0xff KEY_POWER>, <0xf3 KEY_MUTE>, <0xbf KEY_MENU>, <0xf9 0x191>, <0xf5 0x192>, <0xb3 388>, <0xbe KEY_1>, <0xba KEY_2>, <0xb2 KEY_3>, <0xbd KEY_4>, <0xf9 KEY_5>, <0xb1 KEY_6>, <0xfc KEY_7>, <0xf8 KEY_8>, <0xb0 KEY_9>, <0xb6 KEY_0>, <0xb5 KEY_BACKSPACE>; }; }; olt = <3300000>; regulator-always-on; regulator-boot-on; regulator-state-mem { regulator-on-in-suspend; regulator-suspend-microvolt = <3000000>; }; }; vcc28_cif: LDO_REG1 { regulator-name = "vcc28_cif"; regulator-min-microvolt = <2800000>; regulator-max-microvolt = <2800000>; regulator-always-on; regulator-boot-on; regulator-state-mem { regulator-off-in-suspend; }; }; vcc18_cif: LDO_REG2 { regulator-name = "vcc18_cif"; regulator-min-microvolt = <1800000>; regulator-max-microvolt = <1800000>; regulator-always-on; regulator-boot-on; regulator-state-mem { regulator-off-in-suspend; }; }; vdd_11: LDO_REG3 { regulator-name = "vdd_11"; regulator-min-microvolt = <1100000>; regulator-max-microvolt = <1100000>; regulator-always-on; regulator-boot-on; regulator-state-mem { regulator-on-in-suspend; regulator-suspend-microvolt = <1100000>; }; }; ldo4: LDO_REG4 { regulator-name= "ldo4"; regulator-min-microvolt = <3300000>; regulator-max-microvolt = <3300000>; regulator-always-on; regulator-boot-on; regulator-state-mem { regulator-off-in-suspend; }; }; ldo5: LDO_REG5 { regulator-name= "ldo5"; regulator-min-microvolt = <3000000>; regulator-max-microvolt = <3000000>; regulator-always-on; regulator-boot-on; regulator-state-mem { regulator-off-in-suspend; }; }; ldo6: LDO_REG6 { regulator-name= "ldo6"; regulator-min-microvolt = <3300000>; regulator-max-microvolt = <3300000>; regulator-state-mem { regulator-on-in-suspend; regulator-suspend-microvolt = <3300000>; }; }; }; }; }; &lvds { status = "okay"; pinctrl-names = "default"; pinctrl-0 = <&lcdc_lcdc>; ports { lvds_out: port@1 { reg = <1>; #address-cells = <1>; #size-cells = <0>; lvds_out_panel: endpoint@0 { reg = <0>; remote-endpoint = <&panel_in_lvds>; }; }; }; }; &lvds_panel { status = "okay"; compatible ="simple-panel"; backlight = <&backlight>; bus-format = <MEDIA_BUS_FMT_RGB666_1X18>; /* enable-gpios = <&gpio2 10 GPIO_ACTIVE_HIGH>; * delay,disable = <10>; * power-supply = <&vcc_lcd>; */ power-supply = <&ldo6>; power-invert = <1>; rockchip,data-mapping = "jeida"; rockchip,data-width = <18>; rockchip,output = "rgb"; display-timings { native-mode = <&timing0>; timing0: timing0 { clock-frequency = <60000000>; hactive = <1024>; vactive = <600>; hback-porch = <100>; hfront-porch = <120>; vback-porch = <10>; vfront-porch = <15>; hsync-len = <100>; vsync-len = <10>; hsync-active = <0>; vsync-active = <0>; de-active = <0>; pixelclk-active = <0>; }; }; }; &pinctrl { lcdc { lcdc_lcdc: lcdc-lcdc { rockchip,pins = /* depend on the hardware */ <2 RK_PB0 1 &pcfg_pull_none>, /* DCLK */ /* <2 RK_PB1 1 &pcfg_pull_none>, /* HSYNC */ /* <2 RK_PB2 1 &pcfg_pull_none>, /* VSYNC */ <2 RK_PB3 1 &pcfg_pull_none>, /* DEN */ <2 RK_PB4 1 &pcfg_pull_none>, /* DATA10 */ <2 RK_PB5 1 &pcfg_pull_none>, /* DATA11 */ <2 RK_PB6 1 &pcfg_pull_none>, /* DATA12 */ <2 RK_PB7 1 &pcfg_pull_none>, /* DATA13 */ <2 RK_PC0 1 &pcfg_pull_none>, /* DATA14 */ <2 RK_PC1 1 &pcfg_pull_none>, /* DATA15 */ <2 RK_PC2 1 &pcfg_pull_none>, /* DATA16 */ <2 RK_PC3 1 &pcfg_pull_none>; /* DATA17 */ /* <2 RK_PC4 1 &pcfg_pull_none>, /* DATA18 */ /* <2 RK_PC5 1 &pcfg_pull_none>, /* DATA19 */ /* <2 RK_PC6 1 &pcfg_pull_none>, /* DATA20 */ /* <2 RK_PC7 1 &pcfg_pull_none>, /* DATA21 */ /* <2 RK_PD0 1 &pcfg_pull_none>, /* DATA22 */ /* <2 RK_PD1 1 &pcfg_pull_none>; /* DATA23 */ }; }; pmic { pmic_int_l: pmic-int-l { rockchip,pins = <0 2 RK_FUNC_GPIO &pcfg_pull_default>; }; }; }; &pwm0 { status = "okay"; }; &rga { status = "okay"; }; &saradc { status = "okay"; vref-supply = <&vccadc_ref>; }; &sdmmc { cap-mmc-highspeed; supports-sd; broken-cd; card-detect-delay = <800>; ignore-pm-notify; keep-power-in-suspend; cd-gpios = <&gpio1 10 GPIO_ACTIVE_HIGH>; /* CD GPIO */ status = "disabled"; }; &sdio { cap-mmc-highspeed; supports-sdio; ignore-pm-notify; keep-power-in-suspend; non-removable; cap-sdio-irq; status = "disabled"; }; &u2phy { status = "okay"; u2phy_otg: otg-port { status = "okay"; }; u2phy_host: host-port { status = "okay"; }; }; &usb_otg { status = "okay"; }; &vop { status = "okay"; }; &vop_mmu { status = "okay"; }; ; u2phy1_host: host-port { #phy-cells = <0>; interrupts = <GIC_SPI 68 IRQ_TYPE_LEVEL_HIGH>; interrupt-names = "linestate"; status = "disabled"; }; }; power: power-controller { compatible = "rockchip,rk3228-power-controller"; #power-domain-cells = <1>; #address-cells = <1>; #size-cells = <0>; status = "okay"; pd_vpu@RK3228_PD_VPU { reg = <RK3228_PD_VPU>; clocks = <&cru ACLK_VPU>, <&cru HCLK_VPU>; pm_qos = <&qos_vpu>; }; pd_rkvdec@RK3228_PD_RKVDEC { reg = <RK3228_PD_RKVDEC>; clocks = <&cru ACLK_RKVDEC>, <&cru HCLK_RKVDEC>, <&cru SCLK_VDEC_CABAC>, <&cru SCLK_VDEC_CORE>; pm_qos = <&qos_rkvdec_r>, <&qos_rkvdec_w>; }; }; }; uart0: serial@11010000 { compatible = "snps,dw-apb-uart"; reg = <0x11010000 0x100>; interrupts = <GIC_SPI 55 IRQ_TYPE_LEVEL_HIGH>; clock-frequency = <24000000>; clocks = <&cru SCLK_UART0>, <&cru PCLK_UART0>; clock-names = "baudclk", "apb_pclk"; pinctrl-names = "default"; pinctrl-0 = <&uart0_xfer &uart0_cts &uart0_rts>; reg-shift = <2>; reg-io-width = <4>; status = "disabled"; }; uart1: serial@11020000 { compatible = "snps,dw-apb-uart"; reg = <0x11020000 0x100>; interrupts = <GIC_SPI 56 IRQ_TYPE_LEVEL_HIGH>; clock-frequency = <24000000>; clocks = <&cru SCLK_UART1>, <&cru PCLK_UART1>; clock-names = "baudclk", "apb_pclk"; pinctrl-names = "default"; pinctrl-0 = <&uart1_xfer>; reg-shift = <2>; reg-io-width = <4>; status = "disabled"; }; uart2: serial@11030000 { compatible = "snps,dw-apb-uart"; reg = <0x11030000 0x100>; interrupts = <GIC_SPI 57 IRQ_TYPE_LEVEL_HIGH>; clock-frequency = <24000000>; clocks = <&cru SCLK_UART2>, <&cru PCLK_UART2>; clock-names = "baudclk", "apb_pclk"; pinctrl-names = "default"; pinctrl-0 = <&uart21_xfer>; reg-shift = <2>; reg-io-width = <4>; status = "disabled"; }; efuse: efuse@11040000 { compatible = "rockchip,rk322x-efuse"; reg = <0x11040000 0x20>; #address-cells = <1>; #size-cells = <1>; clocks = <&cru PCLK_EFUSE_256>; clock-names = "pclk_efuse"; /* Data cells */ efuse_id: id@7 { reg = <0x7 0x10>; }; cpu_leakage: cpu_leakage@17 { reg = <0x17 0x1>; }; logic_leakage: logic-leakage@19 { reg = <0x19 0x1>; }; hdmi_phy_flag: hdmi_phy_flag@1d { reg = <0x1d 0x1>; bits = <1 1>; }; tve_dac: tve_dac@1d { reg = <0x1d 0x1>; bits = <3 5>; }; }; i2c0: i2c@11050000 { compatible = "rockchip,rk3228-i2c"; reg = <0x11050000 0x1000>; interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>; #address-cells = <1>; #size-cells = <0>; clock-names = "i2c"; clocks = <&cru PCLK_I2C0>; pinctrl-names = "default"; pinctrl-0 = <&i2c0_xfer>; status = "disabled"; }; i2c1: i2c@11060000 { compatible = "rockchip,rk3228-i2c"; reg = <0x11060000 0x1000>; interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>; #address-cells = <1>; #size-cells = <0>; clock-names = "i2c"; clocks = <&cru PCLK_I2C1>; pinctrl-names = "default"; pinctrl-0 = <&i2c1_xfer>; status = "disabled"; }; i2c2: i2c@11070000 { compatible = "rockchip,rk3228-i2c"; reg = <0x11070000 0x1000>; interrupts = <GIC_SPI 38 IRQ_TYPE_LEVEL_HIGH>; #address-cells = <1>; #size-cells = <0>; clock-names = "i2c"; clocks = <&cru PCLK_I2C2>; pinctrl-names = "default"; pinctrl-0 = <&i2c2_xfer>; status = "disabled"; }; i2c3: i2c@11080000 { compatible = "rockchip,rk3228-i2c"; reg = <0x11080000 0x1000>; interrupts = <GIC_SPI 39 IRQ_TYPE_LEVEL_HIGH>; #address-cells = <1>; #size-cells = <0>; clock-names = "i2c"; clocks = <&cru PCLK_I2C3>; pinctrl-names = "default"; pinctrl-0 = <&i2c3_xfer>; status = "disabled"; }; spi0: spi@11090000 { compatible = "rockchip,rk3228-spi"; reg = <0x11090000 0x1000>; interrupts = <GIC_SPI 49 IRQ_TYPE_LEVEL_HIGH>; #address-cells = <1>; #size-cells = <0>; pinctrl-names = "default"; pinctrl-0 = <&spi0_clk &spi0_tx &spi0_rx &spi0_cs0 &spi0_cs1>; clocks = <&cru SCLK_SPI0>, <&cru PCLK_SPI0>; clock-names = "spiclk", "apb_pclk"; status = "disabled"; }; wdt: watchdog@110a0000 { compatible = "rockchip,rk322x-wdt", "snps,dw-wdt"; reg = <0x110a0000 0x100>; clocks = <&cru PCLK_CPU>; interrupts = <GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>; status = "disabled"; }; pwm0: pwm@110b0000 { compatible = "rockchip,rk3288-pwm"; reg = <0x110b0000 0x10>; #pwm-cells = <3>; clocks = <&cru PCLK_PWM>; clock-names = "pwm"; pinctrl-names = "active"; pinctrl-0 = <&pwm0_pin>; status = "disabled"; }; pwm1: pwm@110b0010 { compatible = "rockchip,rk3288-pwm"; reg = <0x110b0010 0x10>; #pwm-cells = <3>; clocks = <&cru PCLK_PWM>; clock-names = "pwm"; pinctrl-names = "active"; pinctrl-0 = <&pwm1_pin>; status = "disabled"; }; pwm2: pwm@110b0020 { compatible = "rockchip,rk3288-pwm"; reg = <0x110b0020 0x10>; #pwm-cells = <3>; clocks = <&cru PCLK_PWM>; clock-names = "pwm"; pinctrl-names = "active"; pinctrl-0 = <&pwm2_pin>; status = "disabled"; }; pwm3: pwm@110b0030 { compatible = "rockchip,rk3288-pwm"; reg = <0x110b0030 0x10>; interrupts = <GIC_SPI 50 IRQ_TYPE_LEVEL_HIGH>; #pwm-cells = <3>; clocks = <&cru PCLK_PWM>; clock-names = "pwm"; pinctrl-names = "active"; pinctrl-0 = <&pwm3_pin>; status = "disabled"; }; timer: timer@110c0000 { compatible = "rockchip,rk3288-timer"; reg = <0x110c0000 0x20>; interrupts = <GIC_SPI 43 IRQ_TYPE_LEVEL_HIGH>; clocks = <&xin24m>, <&cru PCLK_TIMER>; clock-names = "timer", "pclk"; }; cru: clock-controller@110e0000 { compatible = "rockchip,rk3228-cru"; reg = <0x110e0000 0x1000>; rockchip,grf = <&grf>; #clock-cells = <1>; #reset-cells = <1>; assigned-clocks = <&cru PLL_GPLL>, <&cru ARMCLK>, <&cru PLL_CPLL>, <&cru ACLK_PERI>, <&cru HCLK_PERI>, <&cru PCLK_PERI>, <&cru ACLK_CPU>, <&cru HCLK_CPU>, <&cru PCLK_CPU>, <&cru ACLK_VOP>; assigned-clock-rates = <1200000000>, <816000000>, <500000000>, <150000000>, <150000000>, <75000000>, <150000000>, <150000000>, <75000000>, <400000000>; }; thermal_zones: thermal-zones { soc_thermal: soc-thermal { polling-delay-passive = <100>; /* milliseconds */ polling-delay = <5000>; /* milliseconds */ sustainable-power = <1200>; /* milliwatts */ thermal-sensors = <&tsadc 0>; trips { threshold: trip-point@0 { temperature = <70000>; /* millicelsius */ hysteresis = <2000>; /* millicelsius */ type = "passive"; }; target: trip-point@1 { temperature = <85000>; /* millicelsius */ hysteresis = <2000>; /* millicelsius */ type = "passive"; }; soc_crit: soc-crit { temperature = <115000>; /* millicelsius */ hysteresis = <2000>; /* millicelsius */ type = "critical"; }; }; cooling-maps { map0 { trip = <&target>; cooling-device = <&cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; contribution = <1024>; }; map1 { trip = <&target>; cooling-device = <&gpu THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; contribution = <1024>; }; map2 { trip = <&target>; cooling-device = <&dmc THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; contribution = <1024>; }; map3 { trip = <&target>; cooling-device = <&rkvdec THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; contribution = <1024>; }; }; }; }; tsadc: tsadc@11150000 { compatible = "rockchip,rk3228-tsadc"; reg = <0x11150000 0x100>; interrupts = <GIC_SPI 58 IRQ_TYPE_LEVEL_HIGH>; clocks = <&cru SCLK_TSADC>, <&cru PCLK_TSADC>; clock-names = "tsadc", "apb_pclk"; assigned-clocks = <&cru SCLK_TSADC>; assigned-clock-rates = <32768>; resets = <&cru SRST_TSADC>; reset-names = "tsadc-apb"; pinctrl-names = "init", "default", "sleep"; pinctrl-0 = <&otp_gpio>; pinctrl-1 = <&otp_out>; pinctrl-2 = <&otp_gpio>; #thermal-sensor-cells = <0>; rockchip,hw-tshut-temp = <120000>; status = "disabled"; }; codec: codec@12010000 { compatible = "rockchip,rk3228-codec"; reg = <0x12010000 0x1000>; clocks = <&cru SCLK_I2S_OUT>, <&cru PCLK_ACODECPHY>, <&cru SCLK_I2S1>; clock-names = "mclk", "pclk", "sclk"; spk-en-gpio = <&gpio1 RK_PA3 GPIO_ACTIVE_HIGH>; status = "disabled"; }; hdmi_phy: hdmi-phy@12030000 { compatible = "rockchip,rk3228-hdmi-phy"; reg = <0x12030000 0x10000>; #phy-cells = <0>; clocks = <&cru PCLK_HDMI_PHY>, <&xin24m>; clock-names = "sysclk", "refclk"; #clock-cells = <0>; clock-output-names = "hdmiphy_phy"; nvmem-cells = <&hdmi_phy_flag>; nvmem-cell-names = "hdmi_phy_flag"; status = "disabled"; }; gpu: gpu@0x20001000 { compatible = "arm,mali400"; reg = <0x20001000 0x200>, <0x20000000 0x100>, <0x20003000 0x100>, <0x20008000 0x1100>, <0x20004000 0x100>, <0x2000A000 0x1100>, <0x20005000 0x100>; reg-names = "Mali_L2", "Mali_GP", "Mali_GP_MMU", "Mali_PP0", "Mali_PP0_MMU", "Mali_PP1", "Mali_PP1_MMU"; interrupts = <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>; interrupt-names = "Mali_GP_IRQ", "Mali_GP_MMU_IRQ", "Mali_PP0_IRQ", "Mali_PP0_MMU_IRQ", "Mali_PP1_IRQ", "Mali_PP1_MMU_IRQ"; clocks = <&cru ACLK_GPU>; #cooling-cells = <2>; /* min followed by max */ clock-names = "clk_mali"; operating-points-v2 = <&gpu_opp_table>; status = "disabled"; gpu_power_model: power_model { compatible = "arm,mali-simple-power-model"; voltage = <900>; frequency = <500>; static-power = <300>; dynamic-power = <396>; ts = <32000 4700 (-80) 2>; thermal-zone = "soc-thermal"; }; }; gpu_opp_table: opp-table2 { compatible = "operating-points-v2"; rockchip,leakage-voltage-sel = < 1 5 0 6 254 1 >; nvmem-cells = <&logic_leakage>; nvmem-cell-names = "gpu_leakage"; opp-200000000 { opp-hz = /bits/ 64 <200000000>; opp-microvolt = <1050000>; opp-microvolt-L0 = <1050000>; opp-microvolt-L1 = <1000000>; }; opp-300000000 { opp-hz = /bits/ 64 <300000000>; opp-microvolt = <1050000>; opp-microvolt-L0 = <1050000>; opp-microvolt-L1 = <1000000>; }; opp-500000000 { opp-hz = /bits/ 64 <500000000>; opp-microvolt = <1150000>; opp-microvolt-L0 = <1150000>; opp-microvolt-L1 = <1100000>; }; }; vpu_service: vpu-service@20020000 { compatible = "rockchip,vpu_service"; reg = <0x20020000 0x800>; interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>; interrupt-names = "irq_dec", "irq_enc"; resets = <&cru SRST_VPU_A>, <&cru SRST_VPU_H>; reset-names = "video_a", "video_h"; clocks = <&cru ACLK_VPU>, <&cru HCLK_VPU>; clock-names = "aclk_vcodec", "hclk_vcodec"; power-domains = <&power RK3228_PD_VPU>; rockchip,grf = <&grf>; iommus = <&vpu_mmu>; allocator = <1>; status = "disabled"; }; vpu_mmu: iommu@20020800 { compatible = "rockchip,iommu"; reg = <0x20020800 0x40>; interrupts = <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>; interrupt-names = "vpu_mmu"; clock-names = "aclk", "hclk"; clocks = <&cru ACLK_VPU>, <&cru HCLK_VPU>; power-domains = <&power RK3228_PD_VPU>; #iommu-cells = <0>; status = "disabled"; }; rkvdec: rkvdec@20030000 { compatible = "rockchip,rkvdec"; reg = <0x20030000 0x400>; interrupts = <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>; interrupt-names = "irq_dec"; clocks = <&cru ACLK_RKVDEC>, <&cru HCLK_RKVDEC>, <&cru SCLK_VDEC_CABAC>, <&cru SCLK_VDEC_CORE>; clock-names = "aclk_vcodec", "hclk_vcodec", "clk_cabac", "clk_core"; resets = <&cru SRST_RKVDEC_A>, <&cru SRST_RKVDEC_H>, <&cru SRST_RKVDEC_NOC_A>, <&cru SRST_RKVDEC_NOC_H>, <&cru SRST_RKVDEC_CABAC>, <&cru SRST_RKVDEC_CORE>; reset-names = "video_a", "video_h", "niu_a", "niu_h", "video_cabac", "video_core"; power-domains = <&power RK3228_PD_RKVDEC>; operating-points-v2 = <&rkvdec_opp_table>; #cooling-cells = <2>; rockchip,grf = <&grf>; iommus = <&rkvdec_mmu>; allocator = <1>; status = "disabled"; vcodec_power_model: vcodec_power_model { compatible = "vcodec_power_model"; dynamic-power-coefficient = <120>; static-power-coefficient = <200>; ts = <32000 4700 (-80) 2>; thermal-zone = "soc-thermal"; }; }; rkvdec_opp_table: rkvdec-opp-table { compatible = "operating-points-v2"; rockchip,leakage-voltage-sel = < 1 5 0 6 254 1 >; nvmem-cells = <&logic_leakage>; nvmem-cell-names = "rkvdec_leakage"; opp-100000000 { opp-hz = /bits/ 64 <100000000>; opp-microvolt = <1050000>; opp-microvolt-L0 = <1050000>; opp-microvolt-L1 = <1000000>; }; opp-200000000 { opp-hz = /bits/ 64 <200000000>; opp-microvolt = <1050000>; opp-microvolt-L0 = <1050000>; opp-microvolt-L1 = <1000000>; }; opp-500000000 { opp-hz = /bits/ 64 <500000000>; opp-microvolt = <1050000>; opp-microvolt-L0 = <1050000>; opp-microvolt-L1 = <1000000>; }; }; rkvdec_mmu: iommu@20030480 { compatible = "rockchip,iommu"; reg = <0x20030480 0x40>, <0x200304c0 0x40>; interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>; interrupt-names = "rkvdec_mmu"; clocks = <&cru ACLK_RKVDEC>, <&cru HCLK_RKVDEC>; clock-names = "aclk", "hclk"; power-domains = <&power RK3228_PD_RKVDEC>; #iommu-cells = <0>; status = "disabled"; }; vop: vop@20050000 { compatible = "rockchip,rk322x-vop"; reg = <0x20050000 0x1ffc>; reg-names = "regs"; interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>; clocks = <&cru ACLK_VOP>, <&cru DCLK_VOP>, <&cru HCLK_VOP>; clock-names = "aclk_vop", "dclk_vop", "hclk_vop"; resets = <&cru SRST_VOP_A>, <&cru SRST_VOP_H>, <&cru SRST_VOP_D>; reset-names = "axi", "ahb", "dclk"; iommus = <&vop_mmu>; status = "disabled"; vop_out: port { #address-cells = <1>; #size-cells = <0>; vop_out_hdmi: endpoint@0 { reg = <0>; remote-endpoint = <&hdmi_in_vop>; }; vop_out_tve: endpoint@1 { reg = <1>; remote-endpoint = <&tve_in_vop>; }; }; }; vop_mmu: iommu@20050300 { compatible = "rockchip,iommu"; reg = <0x20053f00 0x100>; interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>; interrupt-names = "vop_mmu"; clocks = <&cru ACLK_VOP>, <&cru HCLK_VOP>; clock-names = "aclk", "hclk"; #iommu-cells = <0>; status = "disabled"; }; rk_rga: rk_rga@20060000 { compatible = "rockchip,rga2"; reg = <0x20060000 0x1000>; interrupts = <GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>; clocks = <&cru ACLK_RGA>, <&cru HCLK_RGA>, <&cru SCLK_RGA>; clock-names = "aclk_rga", "hclk_rga", "clk_rga"; dma-coherent; status = "disabled"; }; iep: iep@20070000 { compatible = "rockchip,iep"; iommu_enabled = <1>; iommus = <&iep_mmu>; reg = <0x20070000 0x800>; interrupts = <GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH>; clocks = <&cru ACLK_IEP>, <&cru HCLK_IEP>; clock-names = "aclk_iep", "hclk_iep"; version = <3>; allocator = <1>; status = "disabled"; }; iep_mmu: iommu@20070800 { compatible = "rockchip,iommu"; reg = <0x20070800 0x40>; interrupts = <GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH>; interrupt-names = "iep_mmu"; #iommu-cells = <0>; status = "disabled"; }; display_subsystem: display-subsystem { compatible = "rockchip,display-subsystem"; ports = <&vop_out>; }; hdmi: hdmi@200a0000 { compatible = "rockchip,rk3228-dw-hdmi"; reg = <0x200a0000 0x20000>; reg-io-width = <4>; interrupts = <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 71 IRQ_TYPE_LEVEL_HIGH>; clocks = <&cru SCLK_HDMI_HDCP>, <&cru PCLK_HDMI_CTRL>, <&cru SCLK_HDMI_CEC>; clock-names = "isfr", "iahb", "cec"; pinctrl-names = "default"; pinctrl-0 = <&hdmii2c_xfer &hdmi_hpd &hdmi_cec>; resets = <&cru SRST_HDMI_P>; reset-names = "hdmi"; phys = <&hdmi_phy>; phy-names = "hdmi_phy"; rockchip,grf = <&grf>; status = "disabled"; ports { hdmi_in: port { #address-cells = <1>; #size-cells = <0>; hdmi_in_vop: endpoint@0 { reg = <0>; remote-endpoint = <&vop_out_hdmi>; }; }; }; }; tve: tve@20053e00 { compatible = "rockchip,rk3328-tve"; reg = <0x20053e00 0x100>, <0x12020000 0x10000>; rockchip,saturation = <0x00305b46>; rockchip,brightcontrast = <0x00009900>; rockchip,adjtiming = <0xd6c00880>; rockchip,lumafilter0 = <0x02ff0001>; rockchip,lumafilter1 = <0xf40200fe>; rockchip,lumafilter2 = <0xf332d910>; rockchip,daclevel = <0x15>; rockchip,dac1level = <0x7>; nvmem-cells = <&tve_dac>; nvmem-cell-names = "tve_dac_adj"; status = "disabled"; ports { tve_in: port { #address-cells = <1>; #size-cells = <0>; tve_in_vop: endpoint@0 { reg = <0>; remote-endpoint = <&vop_out_tve>; }; }; }; }; sdmmc: dwmmc@30000000 { compatible = "rockchip,rk3228-dw-mshc", "rockchip,rk3288-dw-mshc"; reg = <0x30000000 0x4000>; interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>; clocks = <&cru HCLK_SDMMC>, <&cru SCLK_SDMMC>, <&cru SCLK_SDMMC_DRV>, <&cru SCLK_SDMMC_SAMPLE>; clock-names = "biu", "ciu", "ciu-drive", "ciu-sample"; fifo-depth = <0x100>; pinctrl-names = "default"; pinctrl-0 = <&sdmmc_clk &sdmmc_cmd &sdmmc_bus4>; status = "disabled"; }; sdio: dwmmc@30010000 { compatible = "rockchip,rk3228-dw-mshc", "rockchip,rk3288-dw-mshc"; reg = <0x30010000 0x4000>; interrupts = <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>; clocks = <&cru HCLK_SDIO>, <&cru SCLK_SDIO>, <&cru SCLK_SDIO_DRV>, <&cru SCLK_SDIO_SAMPLE>; clock-names = "biu", "ciu", "ciu-drive", "ciu-sample"; fifo-depth = <0x100>; pinctrl-names = "default"; pinctrl-0 = <&sdio_clk &sdio_cmd &sdio_bus4>; status = "disabled"; }; emmc: dwmmc@30020000 { compatible = "rockchip,rk3228-dw-mshc", "rockchip,rk3288-dw-mshc"; reg = <0x30020000 0x4000>; interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>; clock-frequency = <37500000>; clock-freq-min-max = <400000 37500000>; clocks = <&cru HCLK_EMMC>, <&cru SCLK_EMMC>, <&cru SCLK_EMMC_DRV>, <&cru SCLK_EMMC_SAMPLE>; clock-names = "biu", "ciu", "ciu-drive", "ciu-sample"; bus-width = <8>; default-sample-phase = <158>; num-slots = <1>; fifo-depth = <0x100>; pinctrl-names = "default"; pinctrl-0 = <&emmc_clk &emmc_cmd &emmc_bus8>; status = "disabled"; }; nandc: nandc@30030000 { compatible = "rockchip,rk-nandc"; reg = <0x30030000 0x4000>; interrupts = <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>; nandc_id = <0>; clocks = <&cru SCLK_NANDC>, <&cru HCLK_NANDC>; clock-names = "clk_nandc", "hclk_nandc"; status = "disabled"; }; usb_otg: usb@30040000 { compatible = "rockchip,rk322x-usb", "rockchip,rk3066-usb", "snps,dwc2"; reg = <0x30040000 0x40000>; interrupts = <GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH>; clocks = <&cru HCLK_OTG>; clock-names = "otg"; dr_mode = "otg"; g-np-tx-fifo-size = <16>; g-rx-fifo-size = <280>; g-tx-fifo-size = <256 128 128 64 32 16>; g-use-dma; phys = <&u2phy0_otg>; phy-names = "usb2-phy"; status = "disabled"; }; usb_host0_ehci: usb@30080000 { compatible = "generic-ehci"; reg = <0x30080000 0x20000>; interrupts = <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>; clocks = <&cru HCLK_HOST0>, <&u2phy0>; clock-names = "usbhost", "utmi"; phys = <&u2phy0_host>; phy-names = "usb"; status = "disabled"; }; usb_host0_ohci: usb@300a0000 { compatible = "generic-ohci"; reg = <0x300a0000 0x20000>; interrupts = <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>; clocks = <&cru HCLK_HOST0>, <&u2phy0>; clock-names = "usbhost", "utmi"; phys = <&u2phy0_host>; phy-names = "usb"; status = "disabled"; }; usb_host1_ehci: usb@300c0000 { compatible = "generic-ehci"; reg = <0x300c0000 0x20000>; interrupts = <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>; clocks = <&cru HCLK_HOST1>, <&u2phy1>; clock-names = "usbhost", "utmi"; phys = <&u2phy1_host>; phy-names = "usb"; status = "disabled"; }; usb_host1_ohci: usb@300e0000 { compatible = "generic-ohci"; reg = <0x300e0000 0x20000>; interrupts = <GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>; clocks = <&cru HCLK_HOST1>, <&u2phy1>; clock-names = "usbhost", "utmi"; phys = <&u2phy1_host>; phy-names = "usb"; status = "disabled"; }; usb_host2_ehci: usb@30100000 { compatible = "generic-ehci"; reg = <0x30100000 0x20000>; interrupts = <GIC_SPI 66 IRQ_TYPE_LEVEL_HIGH>; clocks = <&cru HCLK_HOST2>, <&u2phy1>; phys = <&u2phy1_otg>; phy-names = "usb"; clock-names = "usbhost", "utmi"; status = "disabled"; }; usb_host2_ohci: usb@30120000 { compatible = "generic-ohci"; reg = <0x30120000 0x20000>; interrupts = <GIC_SPI 67 IRQ_TYPE_LEVEL_HIGH>; clocks = <&cru HCLK_HOST2>, <&u2phy1>; clock-names = "usbhost", "utmi"; phys = <&u2phy1_otg>; phy-names = "usb"; status = "disabled"; }; gmac: ethernet@30200000 { compatible = "rockchip,rk3228-gmac"; reg = <0x30200000 0x10000>; interrupts = <GIC_SPI 24 IRQ_TYPE_LEVEL_HIGH>; interrupt-names = "macirq"; clocks = <&cru SCLK_MAC>, <&cru SCLK_MAC_RX>, <&cru SCLK_MAC_TX>, <&cru SCLK_MAC_REF>, <&cru SCLK_MAC_REFOUT>, <&cru ACLK_GMAC>, <&cru PCLK_GMAC>, <&cru SCLK_MAC_PHY>; clock-names = "stmmaceth", "mac_clk_rx", "mac_clk_tx", "clk_mac_ref", "clk_mac_refout", "aclk_mac", "pclk_mac", "clk_macphy"; resets = <&cru SRST_GMAC>, <&cru SRST_MACPHY>; reset-names = "stmmaceth", "mac-phy"; rockchip,grf = <&grf>; status = "disabled"; }; qos_vpu: qos@31040000 { compatible = "syscon"; reg = <0x31040000 0x20>; }; qos_rkvdec_r: qos@31070000 { compatible = "syscon"; reg = <0x31070000 0x20>; }; qos_rkvdec_w: qos@31070080 { compatible = "syscon"; reg = <0x31070080 0x20>; }; gic: interrupt-controller@32010000 { compatible = "arm,gic-400"; interrupt-controller; #interrupt-cells = <3>; #address-cells = <0>; reg = <0x32011000 0x1000>, <0x32012000 0x2000>, <0x32014000 0x2000>, <0x32016000 0x2000>; interrupts = <GIC_PPI 9 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>; }; pinctrl: pinctrl { compatible = "rockchip,rk3228-pinctrl"; rockchip,grf = <&grf>; #address-cells = <1>; #size-cells = <1>; ranges; gpio0: gpio0@11110000 { compatible = "rockchip,gpio-bank"; reg = <0x11110000 0x100>; interrupts = <GIC_SPI 51 IRQ_TYPE_LEVEL_HIGH>; clocks = <&cru PCLK_GPIO0>; gpio-controller; #gpio-cells = <2>; interrupt-controller; #interrupt-cells = <2>; }; gpio1: gpio1@11120000 { compatible = "rockchip,gpio-bank"; reg = <0x11120000 0x100>; interrupts = <GIC_SPI 52 IRQ_TYPE_LEVEL_HIGH>; clocks = <&cru PCLK_GPIO1>; gpio-controller; #gpio-cells = <2>; interrupt-controller; #interrupt-cells = <2>; }; gpio2: gpio2@11130000 { compatible = "rockchip,gpio-bank"; reg = <0x11130000 0x100>; interrupts = <GIC_SPI 53 IRQ_TYPE_LEVEL_HIGH>; clocks = <&cru PCLK_GPIO2>; gpio-controller; #gpio-cells = <2>; interrupt-controller; #interrupt-cells = <2>; }; gpio3: gpio3@11140000 { compatible = "rockchip,gpio-bank"; reg = <0x11140000 0x100>; interrupts = <GIC_SPI 54 IRQ_TYPE_LEVEL_HIGH>; clocks = <&cru PCLK_GPIO3>; gpio-controller; #gpio-cells = <2>; interrupt-controller; #interrupt-cells = <2>; }; pcfg_pull_up: pcfg-pull-up { bias-pull-up; }; pcfg_pull_down: pcfg-pull-down { bias-pull-down; }; pcfg_pull_none: pcfg-pull-none { bias-disable; }; pcfg_pull_none_drv_12ma: pcfg-pull-none-drv-12ma { drive-strength = <12>; }; sdmmc { sdmmc_clk: sdmmc-clk { rockchip,pins = <1 16 RK_FUNC_1 &pcfg_pull_none_drv_12ma>; }; sdmmc_cmd: sdmmc-cmd { rockchip,pins = <1 15 RK_FUNC_1 &pcfg_pull_none_drv_12ma>; }; sdmmc_bus4: sdmmc-bus4 { rockchip,pins = <1 18 RK_FUNC_1 &pcfg_pull_none_drv_12ma>, <1 19 RK_FUNC_1 &pcfg_pull_none_drv_12ma>, <1 20 RK_FUNC_1 &pcfg_pull_none_drv_12ma>, <1 21 RK_FUNC_1 &pcfg_pull_none_drv_12ma>; }; }; sdio { sdio_clk: sdio-clk { rockchip,pins = <3 0 RK_FUNC_1 &pcfg_pull_none_drv_12ma>; }; sdio_cmd: sdio-cmd { rockchip,pins = <3 1 RK_FUNC_1 &pcfg_pull_none_drv_12ma>; }; sdio_bus4: sdio-bus4 { rockchip,pins = <3 2 RK_FUNC_1 &pcfg_pull_none_drv_12ma>, <3 3 RK_FUNC_1 &pcfg_pull_none_drv_12ma>, <3 4 RK_FUNC_1 &pcfg_pull_none_drv_12ma>, <3 5 RK_FUNC_1 &pcfg_pull_none_drv_12ma>; }; }; emmc { emmc_clk: emmc-clk { rockchip,pins = <2 7 RK_FUNC_2 &pcfg_pull_none>; }; emmc_cmd: emmc-cmd { rockchip,pins = <1 22 RK_FUNC_2 &pcfg_pull_none>; }; emmc_bus8: emmc-bus8 { rockchip,pins = <1 24 RK_FUNC_2 &pcfg_pull_none>, <1 25 RK_FUNC_2 &pcfg_pull_none>, <1 26 RK_FUNC_2 &pcfg_pull_none>, <1 27 RK_FUNC_2 &pcfg_pull_none>, <1 28 RK_FUNC_2 &pcfg_pull_none>, <1 29 RK_FUNC_2 &pcfg_pull_none>, <1 30 RK_FUNC_2 &pcfg_pull_none>, <1 31 RK_FUNC_2 &pcfg_pull_none>; }; }; gmac { rgmii_pins: rgmii-pins { rockchip,pins = <2 14 RK_FUNC_1 &pcfg_pull_none>, <2 12 RK_FUNC_1 &pcfg_pull_none>, <2 25 RK_FUNC_1 &pcfg_pull_none>, <2 19 RK_FUNC_1 &pcfg_pull_none_drv_12ma>, <2 18 RK_FUNC_1 &pcfg_pull_none_drv_12ma>, <2 22 RK_FUNC_1 &pcfg_pull_none_drv_12ma>, <2 23 RK_FUNC_1 &pcfg_pull_none_drv_12ma>, <2 9 RK_FUNC_1 &pcfg_pull_none_drv_12ma>, <2 13 RK_FUNC_1 &pcfg_pull_none_drv_12ma>, <2 17 RK_FUNC_1 &pcfg_pull_none>, <2 16 RK_FUNC_1 &pcfg_pull_none>, <2 21 RK_FUNC_2 &pcfg_pull_none>, <2 20 RK_FUNC_2 &pcfg_pull_none>, <2 11 RK_FUNC_1 &pcfg_pull_none>, <2 8 RK_FUNC_1 &pcfg_pull_none>; }; rmii_pins: rmii-pins { rockchip,pins = <2 14 RK_FUNC_1 &pcfg_pull_none>, <2 12 RK_FUNC_1 &pcfg_pull_none>, <2 25 RK_FUNC_1 &pcfg_pull_none>, <2 19 RK_FUNC_1 &pcfg_pull_none_drv_12ma>, <2 18 RK_FUNC_1 &pcfg_pull_none_drv_12ma>, <2 13 RK_FUNC_1 &pcfg_pull_none_drv_12ma>, <2 17 RK_FUNC_1 &pcfg_pull_none>, <2 16 RK_FUNC_1 &pcfg_pull_none>, <2 8 RK_FUNC_1 &pcfg_pull_none>, <2 15 RK_FUNC_1 &pcfg_pull_none>; }; phy_pins: phy-pins { rockchip,pins = <2 14 RK_FUNC_2 &pcfg_pull_none>, <2 8 RK_FUNC_2 &pcfg_pull_none>; }; }; hdmi { hdmi_hpd: hdmi-hpd { rockchip,pins = <0 15 RK_FUNC_1 &pcfg_pull_down>; }; hdmii2c_xfer: hdmii2c-xfer { rockchip,pins = <0 6 RK_FUNC_2 &pcfg_pull_none>, <0 7 RK_FUNC_2 &pcfg_pull_none>; }; hdmi_cec: hdmi-cec { rockchip,pins = <0 RK_PC4 RK_FUNC_1 &pcfg_pull_none>; }; }; i2c0 { i2c0_xfer: i2c0-xfer { rockchip,pins = <0 0 RK_FUNC_1 &pcfg_pull_none>, <0 1 RK_FUNC_1 &pcfg_pull_none>; }; }; i2c1 { i2c1_xfer: i2c1-xfer { rockchip,pins = <0 2 RK_FUNC_1 &pcfg_pull_none>, <0 3 RK_FUNC_1 &pcfg_pull_none>; }; }; i2c2 { i2c2_xfer: i2c2-xfer { rockchip,pins = <2 20 RK_FUNC_1 &pcfg_pull_none>, <2 21 RK_FUNC_1 &pcfg_pull_none>; }; }; i2c3 { i2c3_xfer: i2c3-xfer { rockchip,pins = <0 6 RK_FUNC_1 &pcfg_pull_none>, <0 7 RK_FUNC_1 &pcfg_pull_none>; }; }; tsp { tsp_d0: tsp-d0 { rockchip,pins = <2 19 RK_FUNC_2 &pcfg_pull_none>; }; tsp_d1: tsp-d1 { rockchip,pins = <2 18 RK_FUNC_2 &pcfg_pull_none>; }; tsp_d2: tsp-d2 { rockchip,pins = <2 17 RK_FUNC_2 &pcfg_pull_none>; }; tsp_d3: tsp-d3 { rockchip,pins = <2 16 RK_FUNC_2 &pcfg_pull_none>; }; tsp_d4: tsp-d4 { rockchip,pins = <2 25 RK_FUNC_2 &pcfg_pull_none>; }; tsp_d5: tsp-d5 { rockchip,pins = <2 24 RK_FUNC_2 &pcfg_pull_none>; }; tsp_d6: tsp-d6 { rockchip,pins = <2 15 RK_FUNC_2 &pcfg_pull_none>; }; tsp_d7: tsp-d7 { rockchip,pins = <2 13 RK_FUNC_2 &pcfg_pull_none>; }; tsp_sync: tsp-sync { rockchip,pins = <2 12 RK_FUNC_2 &pcfg_pull_none>; }; tsp_clk: tsp-clk { rockchip,pins = <2 11 RK_FUNC_2 &pcfg_pull_none>; }; tsp_fail: tsp-fail { rockchip,pins = <2 10 RK_FUNC_2 &pcfg_pull_none>; }; tsp_valid: tsp-valid { rockchip,pins = <2 9 RK_FUNC_2 &pcfg_pull_none>; }; }; spi-0 { spi0_clk: spi0-clk { rockchip,pins = <0 9 RK_FUNC_2 &pcfg_pull_up>; }; spi0_cs0: spi0-cs0 { rockchip,pins = <0 14 RK_FUNC_2 &pcfg_pull_up>; }; spi0_tx: spi0-tx { rockchip,pins = <0 11 RK_FUNC_2 &pcfg_pull_up>; }; spi0_rx: spi0-rx { rockchip,pins = <0 13 RK_FUNC_2 &pcfg_pull_up>; }; spi0_cs1: spi0-cs1 { rockchip,pins = <1 12 RK_FUNC_1 &pcfg_pull_up>; }; }; spi-1 { spi1_clk: spi1-clk { rockchip,pins = <0 23 RK_FUNC_2 &pcfg_pull_up>; }; spi1_cs0: spi1-cs0 { rockchip,pins = <2 2 RK_FUNC_2 &pcfg_pull_up>; }; spi1_rx: spi1-rx { rockchip,pins = <2 0 RK_FUNC_2 &pcfg_pull_up>; }; spi1_tx: spi1-tx { rockchip,pins = <2 1 RK_FUNC_2 &pcfg_pull_up>; }; spi1_cs1: spi1-cs1 { rockchip,pins = <2 3 RK_FUNC_2 &pcfg_pull_up>; }; }; i2s1 { i2s1_bus: i2s1-bus { rockchip,pins = <0 8 RK_FUNC_1 &pcfg_pull_none>, <0 9 RK_FUNC_1 &pcfg_pull_none>, <0 11 RK_FUNC_1 &pcfg_pull_none>, <0 12 RK_FUNC_1 &pcfg_pull_none>, <0 13 RK_FUNC_1 &pcfg_pull_none>, <0 14 RK_FUNC_1 &pcfg_pull_none>, <1 2 RK_FUNC_2 &pcfg_pull_none>, <1 4 RK_FUNC_2 &pcfg_pull_none>, <1 5 RK_FUNC_2 &pcfg_pull_none>; }; }; pwm0 { pwm0_pin: pwm0-pin { rockchip,pins = <3 21 RK_FUNC_1 &pcfg_pull_none>; }; pwm0_pin_pull_down: pwm0-pin-pull-down { rockchip,pins = <3 21 RK_FUNC_1 &pcfg_pull_down>; }; }; pwm1 { pwm1_pin: pwm1-pin { rockchip,pins = <0 30 RK_FUNC_2 &pcfg_pull_none>; }; pwm1_pin_pull_down: pwm1-pin-pull-down { rockchip,pins = <0 30 RK_FUNC_2 &pcfg_pull_down>; }; }; pwm2 { pwm2_pin: pwm2-pin { rockchip,pins = <1 12 RK_FUNC_2 &pcfg_pull_none>; }; pwm2_pin_pull_up: pwm2-pin-pull-up { rockchip,pins = <1 12 RK_FUNC_2 &pcfg_pull_up>; }; }; pwm3 { pwm3_pin: pwm3-pin { rockchip,pins = <1 11 RK_FUNC_2 &pcfg_pull_none>; }; pwm3_pin_pull_down: pwm3-pin-pull-down { rockchip,pins = <1 11 RK_FUNC_2 &pcfg_pull_down>; }; }; spdif { spdif_tx: spdif-tx { rockchip,pins = <3 31 RK_FUNC_2 &pcfg_pull_none>; }; }; tsadc { otp_gpio: otp-gpio { rockchip,pins = <0 24 RK_FUNC_GPIO &pcfg_pull_none>; }; otp_out: otp-out { rockchip,pins = <0 24 RK_FUNC_2 &pcfg_pull_none>; }; }; uart0 { uart0_xfer: uart0-xfer { rockchip,pins = <2 26 RK_FUNC_1 &pcfg_pull_none>, <2 27 RK_FUNC_1 &pcfg_pull_none>; }; uart0_cts: uart0-cts { rockchip,pins = <2 29 RK_FUNC_1 &pcfg_pull_none>; }; uart0_rts: uart0-rts { rockchip,pins = <0 17 RK_FUNC_1 &pcfg_pull_none>; }; }; uart1 { uart1_xfer: uart1-xfer { rockchip,pins = <1 9 RK_FUNC_1 &pcfg_pull_none>, <1 10 RK_FUNC_1 &pcfg_pull_none>; }; uart1_cts: uart1-cts { rockchip,pins = <1 8 RK_FUNC_1 &pcfg_pull_none>; }; uart1_rts: uart1-rts { rockchip,pins = <1 11 RK_FUNC_1 &pcfg_pull_none>; }; }; uart1-1 { uart11_xfer: uart11-xfer { rockchip,pins = <3 14 RK_FUNC_1 &pcfg_pull_up>, <3 13 RK_FUNC_1 &pcfg_pull_none>; }; uart11_cts: uart11-cts { rockchip,pins = <3 7 RK_FUNC_1 &pcfg_pull_none>; }; uart11_rts: uart11-rts { rockchip,pins = <3 6 RK_FUNC_1 &pcfg_pull_none>; }; uart11_rts_gpio: uart11-rts-gpio { rockchip,pins = <3 6 RK_FUNC_GPIO &pcfg_pull_none>; }; }; uart2 { uart2_xfer: uart2-xfer { rockchip,pins = <1 18 RK_FUNC_2 &pcfg_pull_up>, <1 19 RK_FUNC_2 &pcfg_pull_none>; }; uart2_cts: uart2-cts { rockchip,pins = <0 25 RK_FUNC_1 &pcfg_pull_none>; }; uart2_rts: uart2-rts { rockchip,pins = <0 24 RK_FUNC_1 &pcfg_pull_none>; }; }; uart2-1 { uart21_xfer: uart21-xfer { rockchip,pins = <1 10 RK_FUNC_2 &pcfg_pull_up>, <1 9 RK_FUNC_2 &pcfg_pull_none>; }; }; }; rockchip_suspend: rockchip-suspend { compatible = "rockchip,pm-rk322x"; status = "disabled"; rockchip,virtual-poweroff = <0>; rockchip,sleep-mode-config = < (0 |RKPM_CTR_GTCLKS |RKPM_CTR_IDLESRAM_MD ) >; }; }; ; rockchip,bits = <0 5>; clocks = <&clk_vepu>; clock-output-names = "clk_vepu"; rockchip,div-type = <CLK_DIVIDER_PLUS_ONE>; #clock-cells = <0>; rockchip,clkops-idx = <CLKOPS_RATE_MUX_DIV>; }; /* reg[5]: reserved */ clk_vepu: clk_vepu_mux { compatible = "rockchip,rk3188-mux-con"; rockchip,bits = <6 2>; clocks = <&dummy_cpll>, <&clk_gpll>, <&usbphy_480m>; clock-output-names = "clk_vepu"; #clock-cells = <0>; #clock-init-cells = <1>; }; clk_vdpu_div: clk_vdpu_div { compatible = "rockchip,rk3188-div-con"; rockchip,bits = <8 5>; clocks = <&clk_vdpu>; clock-output-names = "clk_vdpu"; rockchip,div-type = <CLK_DIVIDER_PLUS_ONE>; #clock-cells = <0>; rockchip,clkops-idx = <CLKOPS_RATE_MUX_DIV>; }; /* reg[13]: reserved */ clk_vdpu: clk_vdpu_mux { compatible = "rockchip,rk3188-mux-con"; rockchip,bits = <14 2>; clocks = <&dummy_cpll>, <&clk_gpll>, <&usbphy_480m>; clock-output-names = "clk_vdpu"; #clock-cells = <0>; #clock-init-cells = <1>; }; }; clk_sel_con33: sel-con@00e4 { compatible = "rockchip,rk3188-selcon"; reg = <0x00e4 0x4>; #address-cells = <1>; #size-cells = <1>; pclk_pd_pmu: pclk_pd_pmu_div { compatible = "rockchip,rk3188-div-con"; rockchip,bits = <0 5>; clocks = <&clk_gpll>; clock-output-names = "pclk_pd_pmu"; rockchip,div-type = <CLK_DIVIDER_PLUS_ONE>; #clock-cells = <0>; #clock-init-cells = <1>; }; /* reg[7:5]: reserved */ pclk_pd_alive: pclk_pd_alive { compatible = "rockchip,rk3188-div-con"; rockchip,bits = <8 5>; clocks = <&clk_gpll>; clock-output-names = "pclk_pd_alive"; rockchip,div-type = <CLK_DIVIDER_PLUS_ONE>; #clock-cells = <0>; #clock-init-cells = <1>; }; /* reg[15:13]: reserved */ }; clk_sel_con34: sel-con@00e8 { compatible = "rockchip,rk3188-selcon"; reg = <0x00e8 0x4>; #address-cells = <1>; #size-cells = <1>; clk_gpu_div: clk_gpu_div { compatible = "rockchip,rk3188-div-con"; rockchip,bits = <0 5>; clocks = <&clk_gpu>; clock-output-names = "clk_gpu"; rockchip,div-type = <CLK_DIVIDER_PLUS_ONE>; #clock-cells = <0>; rockchip,clkops-idx = <CLKOPS_RATE_MUX_DIV>; rockchip,flags = <CLK_SET_RATE_PARENT_IN_ORDER>; }; /* reg[5]: reserved */ clk_gpu: clk_gpu_mux { compatible = "rockchip,rk3188-mux-con"; rockchip,bits = <6 2>; clocks = <&dummy_cpll>, <&clk_gpll>, <&usbphy_480m>, <&clk_npll>; clock-output-names = "clk_gpu"; #clock-cells = <0>; #clock-init-cells = <1>; }; clk_sdio1_div: clk_sdio1_div { compatible = "rockchip,rk3188-div-con"; rockchip,bits = <8 6>; clocks = <&clk_sdio1>; clock-output-names = "clk_sdio1"; rockchip,div-type = <CLK_DIVIDER_PLUS_ONE>; #clock-cells = <0>; rockchip,clkops-idx = <CLKOPS_RATE_MUX_EVENDIV>; }; clk_sdio1: clk_sdio1_mux { compatible = "rockchip,rk3188-mux-con"; rockchip,bits = <14 2>; clocks = <&dummy_cpll>, <&clk_gpll>, <&xin24m>; clock-output-names = "clk_sdio1"; #clock-cells = <0>; }; }; clk_sel_con35: sel-con@00ec { compatible = "rockchip,rk3188-selcon"; reg = <0x00ec 0x4>; #address-cells = <1>; #size-cells = <1>; clk_tsp_div: clk_tsp_div { compatible = "rockchip,rk3188-div-con"; rockchip,bits = <0 5>; clocks = <&clk_tsp>; clock-output-names = "clk_tsp"; rockchip,div-type = <CLK_DIVIDER_PLUS_ONE>; #clock-cells = <0>; rockchip,clkops-idx = <CLKOPS_RATE_MUX_DIV>; }; /* reg[5]: reserved */ clk_tsp: clk_tsp_mux { compatible = "rockchip,rk3188-mux-con"; rockchip,bits = <6 2>; clocks = <&dummy_cpll>, <&clk_gpll>, <&clk_npll>; clock-output-names = "clk_tsp"; #clock-cells = <0>; #clock-init-cells = <1>; }; clk_tspout_div: clk_tspout_div { compatible = "rockchip,rk3188-div-con"; rockchip,bits = <8 5>; clocks = <&clk_tspout>; clock-output-names = "clk_tspout"; rockchip,div-type = <CLK_DIVIDER_PLUS_ONE>; #clock-cells = <0>; rockchip,clkops-idx = <CLKOPS_RATE_MUX_DIV>; }; /* reg[13]: reserved */ clk_tspout: clk_tspout_mux { compatible = "rockchip,rk3188-mux-con"; rockchip,bits = <14 2>; clocks = <&dummy_cpll>, <&clk_gpll>, <&clk_npll>, <&io_27m_in>; clock-output-names = "clk_tspout"; #clock-cells = <0>; #clock-init-cells = <1>; }; }; clk_sel_con36: sel-con@00f0 { compatible = "rockchip,rk3188-selcon"; reg = <0x00f0 0x4>; #address-cells = <1>; #size-cells = <1>; clk_core0: clk_core0_div { compatible = "rockchip,rk3188-div-con"; rockchip,bits = <0 3>; clocks = <&clk_core>; clock-output-names = "clk_core0"; rockchip,div-type = <CLK_DIVIDER_PLUS_ONE>; #clock-cells = <0>; rockchip,clkops-idx = <CLKOPS_RATE_CORE_CHILD>; }; /* reg[3]: reserved */ clk_core1: clk_core1_div { compatible = "rockchip,rk3188-div-con"; rockchip,bits = <4 3>; clocks = <&clk_core>; clock-output-names = "clk_core1"; rockchip,div-type = <CLK_DIVIDER_PLUS_ONE>; #clock-cells = <0>; rockchip,clkops-idx = <CLKOPS_RATE_CORE_CHILD>; }; /* reg[7]: reserved */ clk_core2: clk_core2_div { compatible = "rockchip,rk3188-div-con"; rockchip,bits = <8 3>; clocks = <&clk_core>; clock-output-names = "clk_core2"; rockchip,div-type = <CLK_DIVIDER_PLUS_ONE>; #clock-cells = <0>; rockchip,clkops-idx = <CLKOPS_RATE_CORE_CHILD>; }; /* reg[11]: reserved */ clk_core3: clk_core3_div { compatible = "rockchip,rk3188-div-con"; rockchip,bits = <12 3>; clocks = <&clk_core>; clock-output-names = "clk_core3"; rockchip,div-type = <CLK_DIVIDER_PLUS_ONE>; #clock-cells = <0>; rockchip,clkops-idx = <CLKOPS_RATE_CORE_CHILD>; }; /* reg[15]: reserved */ }; clk_sel_con37: sel-con@00f4 { compatible = "rockchip,rk3188-selcon"; reg = <0x00f4 0x4>; #address-cells = <1>; #size-cells = <1>; clk_l2ram: clk_l2ram_div { compatible = "rockchip,rk3188-div-con"; rockchip,bits = <0 3>; clocks = <&clk_core>; clock-output-names = "clk_l2ram"; rockchip,div-type = <CLK_DIVIDER_PLUS_ONE>; #clock-cells = <0>; rockchip,clkops-idx = <CLKOPS_RATE_CORE_CHILD>; }; /* reg[3]: reserved */ atclk_core: atclk_core_div { compatible = "rockchip,rk3188-div-con"; rockchip,bits = <4 5>; clocks = <&clk_core>; clock-output-names = "atclk_core"; rockchip,div-type = <CLK_DIVIDER_PLUS_ONE>; #clock-cells = <0>; rockchip,clkops-idx = <CLKOPS_RATE_CORE_CHILD>; }; pclk_dbg_src: pclk_core_dbg_div { compatible = "rockchip,rk3188-div-con"; rockchip,bits = <9 5>; clocks = <&clk_core>; clock-output-names = "pclk_dbg_src"; rockchip,div-type = <CLK_DIVIDER_PLUS_ONE>; #clock-cells = <0>; rockchip,clkops-idx = <CLKOPS_RATE_CORE_CHILD>; }; /* reg[15:14]: reserved */ }; clk_sel_con38: sel-con@00f8 { compatible = "rockchip,rk3188-selcon"; reg = <0x00f8 0x4>; #address-cells = <1>; #size-cells = <1>; clk_nandc0_div: clk_nandc0_div { compatible = "rockchip,rk3188-div-con"; rockchip,bits = <0 5>; clocks = <&clk_nandc0>; clock-output-names = "clk_nandc0"; rockchip,div-type = <CLK_DIVIDER_PLUS_ONE>; #clock-cells = <0>; rockchip,clkops-idx = <CLKOPS_RATE_MUX_DIV>; }; /* reg[6:5]: reserved */ clk_nandc0: clk_nandc0_mux { compatible = "rockchip,rk3188-mux-con"; rockchip,bits = <7 1>; clocks = <&dummy_cpll>, <&clk_gpll>; clock-output-names = "clk_nandc0"; #clock-cells = <0>; }; clk_nandc1_div: clk_nandc1_div { compatible = "rockchip,rk3188-div-con"; rockchip,bits = <8 5>; clocks = <&clk_nandc1>; clock-output-names = "clk_nandc1"; rockchip,div-type = <CLK_DIVIDER_PLUS_ONE>; #clock-cells = <0>; rockchip,clkops-idx = <CLKOPS_RATE_MUX_DIV>; }; /* reg[14:13]: reserved */ clk_nandc1: clk_nandc1_mux { compatible = "rockchip,rk3188-mux-con"; rockchip,bits = <15 1>; clocks = <&dummy_cpll>, <&clk_gpll>; clock-output-names = "clk_nandc1"; #clock-cells = <0>; }; }; clk_sel_con39: sel-con@00fc { compatible = "rockchip,rk3188-selcon"; reg = <0x00fc 0x4>; #address-cells = <1>; #size-cells = <1>; clk_spi2_div: clk_spi2_div { compatible = "rockchip,rk3188-div-con"; rockchip,bits = <0 7>; clocks = <&clk_spi2>; clock-output-names = "clk_spi2"; rockchip,div-type = <CLK_DIVIDER_PLUS_ONE>; #clock-cells = <0>; rockchip,clkops-idx = <CLKOPS_RATE_MUX_DIV>; }; clk_spi2: clk_spi2_mux { compatible = "rockchip,rk3188-mux-con"; rockchip,bits = <7 1>; clocks = <&dummy_cpll>, <&clk_gpll>; clock-output-names = "clk_spi2"; #clock-cells = <0>; }; aclk_hevc_div: aclk_hevc_div { compatible = "rockchip,rk3188-div-con"; rockchip,bits = <8 5>; clocks = <&aclk_hevc>; clock-output-names = "aclk_hevc"; rockchip,div-type = <CLK_DIVIDER_PLUS_ONE>; #clock-cells = <0>; rockchip,clkops-idx = <CLKOPS_RATE_MUX_DIV>; rockchip,flags = <CLK_SET_RATE_PARENT_IN_ORDER>; }; /* reg[13]: reserved */ aclk_hevc: aclk_hevc_mux { compatible = "rockchip,rk3188-mux-con"; rockchip,bits = <14 2>; clocks = <&dummy_cpll>, <&clk_gpll>, <&clk_npll>; clock-output-names = "aclk_hevc"; #clock-cells = <0>; #clock-init-cells = <1>; }; }; clk_sel_con40: sel-con@0100 { compatible = "rockchip,rk3188-selcon"; reg = <0x0100 0x4>; #address-cells = <1>; #size-cells = <1>; spdif_8ch_div: spdif_8ch_div { compatible = "rockchip,rk3188-div-con"; rockchip,bits = <0 7>; clocks = <&clk_spdif_pll>; clock-output-names = "spdif_8ch_div"; rockchip,div-type = <CLK_DIVIDER_PLUS_ONE>; #clock-cells = <0>; }; /* reg[7]: reserved */ clk_spdif_8ch: spdif_8ch_clk_mux { compatible = "rockchip,rk3188-mux-con"; rockchip,bits = <8 2>; clocks = <&spdif_8ch_div>, <&spdif_8ch_frac>, <&xin12m>; clock-output-names = "clk_spdif_8ch"; #clock-cells = <0>; rockchip,clkops-idx = <CLKOPS_RATE_RK3288_I2S>; rockchip,flags = <CLK_SET_RATE_PARENT>; }; /* reg[11:10]: reserved */ hclk_hevc: hclk_hevc_div { compatible = "rockchip,rk3188-div-con"; rockchip,bits = <12 2>; clocks = <&aclk_hevc>; clock-output-names = "hclk_hevc"; rockchip,div-type = <CLK_DIVIDER_PLUS_ONE>; #clock-cells = <0>; #clock-init-cells = <1>; }; /* reg[15:14]: reserved */ }; clk_sel_con41: sel-con@0104 { compatible = "rockchip,rk3188-selcon"; reg = <0x0104 0x4>; #address-cells = <1>; #size-cells = <1>; spdif_8ch_frac: spdif_8ch_frac { compatible = "rockchip,rk3188-frac-con"; clocks = <&spdif_8ch_div>; clock-output-names = "spdif_8ch_frac"; /* numerator denominator */ rockchip,bits = <0 32>; rockchip,clkops-idx = <CLKOPS_RATE_FRAC>; #clock-cells = <0>; }; }; clk_sel_con42: sel-con@0108 { compatible = "rockchip,rk3188-selcon"; reg = <0x0108 0x4>; #address-cells = <1>; #size-cells = <1>; clk_hevc_cabac_div: clk_hevc_cabac_div { compatible = "rockchip,rk3188-div-con"; rockchip,bits = <0 5>; clocks = <&clk_hevc_cabac>; clock-output-names = "clk_hevc_cabac"; rockchip,div-type = <CLK_DIVIDER_PLUS_ONE>; #clock-cells = <0>; rockchip,clkops-idx = <CLKOPS_RATE_MUX_DIV>; rockchip,flags = <CLK_SET_RATE_PARENT_IN_ORDER>; }; /* reg[5]: reserved */ clk_hevc_cabac: clk_hevc_cabac_mux { compatible = "rockchip,rk3188-mux-con"; rockchip,bits = <6 2>; clocks = <&dummy_cpll>, <&clk_gpll>, <&clk_npll>; clock-output-names = "clk_hevc_cabac"; #clock-cells = <0>; #clock-init-cells = <1>; }; clk_hevc_core_div: clk_hevc_core_div { compatible = "rockchip,rk3188-div-con"; rockchip,bits = <8 5>; clocks = <&clk_hevc_core>; clock-output-names = "clk_hevc_core"; rockchip,div-type = <CLK_DIVIDER_PLUS_ONE>; #clock-cells = <0>; rockchip,clkops-idx = <CLKOPS_RATE_MUX_DIV>; rockchip,flags = <CLK_SET_RATE_PARENT_IN_ORDER>; }; /* reg[13]: reserved */ clk_hevc_core: clk_hevc_core_mux { compatible = "rockchip,rk3188-mux-con"; rockchip,bits = <14 2>; clocks = <&dummy_cpll>, <&clk_gpll>, <&clk_npll>; clock-output-names = "clk_hevc_core"; #clock-cells = <0>; #clock-init-cells = <1>; }; }; }; /* Gate control regs */ clk_gate_cons { compatible = "rockchip,rk-gate-cons"; #address-cells = <1>; #size-cells = <1>; ranges ; clk_gates0: gate-clk@0160 { compatible = "rockchip,rk3188-gate-clk"; reg = <0x0160 0x4>; clocks = <&dummy>, <&clk_apll>, <&clk_gpll>, <&aclk_bus>, <&hclk_bus>, <&pclk_bus>, <&dummy>, <&aclk_bus>, <&clk_dpll>, <&clk_gpll>, <&clk_gpll>, <&clk_cpll>, <&xin24m>, <&dummy>, <&dummy>, <&dummy>; clock-output-names = "reserved", "reserved", /* do not use bit1 = "core_apll" */ "clk_arm_gpll", "g_aclk_bus", "hclk_bus", "pclk_bus", "reserved", "aclk_bus_2pmu", "reserved", "reserved", /*"clk_ddr_dpll", "clk_ddr_gpll",*/ "reserved", "reserved", /*"clk_bus_gpll", "clk_bus_cpll",*/ "clk_acc_efuse", "reserved", "reserved", "reserved"; rockchip,suspend-clkgating-setting=<0x0fff 0x0fff>; #clock-cells = <1>; }; clk_gates1: gate-clk@0164 { compatible = "rockchip,rk3188-gate-clk"; reg = <0x0164 0x4>; clocks = <&xin24m>, <&xin24m>, <&xin24m>, <&xin24m>, <&xin24m>, <&xin24m>, <&dummy>, <&dummy>, <&clk_uart0_pll>, <&uart0_frac>, <&clk_uart1_div>, <&uart1_frac>, <&clk_uart2_div>, <&uart2_frac>, <&clk_uart3_div>, <&uart3_frac>; clock-output-names = "clk_timer0", "clk_timer1", "clk_timer2", "clk_timer3", "clk_timer4", "clk_timer5", "reserved", "reserved", "clk_uart0_pll", "uart0_frac", "clk_uart1_div", "uart1_frac", "clk_uart2_div", "uart2_frac", "clk_uart3_div", "uart3_frac"; rockchip,suspend-clkgating-setting=<0x0 0x0>; #clock-cells = <1>; }; clk_gates2: gate-clk@0168 { compatible = "rockchip,rk3188-gate-clk"; reg = <0x0168 0x4>; clocks = <&aclk_peri>, <&aclk_peri>, <&hclk_peri>, <&pclk_peri>, <&dummy>, <&clk_mac_pll>, <&clk_hsadc_pll>, <&clk_tsadc>, <&clk_saradc>, <&clk_spi0>, <&clk_spi1>, <&clk_spi2>, <&clk_uart4_div>, <&uart4_frac>, <&dummy>, <&dummy>; clock-output-names = "aclk_peri", "reserved", /*"g_aclk_periph",*/ "hclk_peri", "pclk_peri", "reserved", "clk_mac_pll", "clk_hsadc_pll", "clk_tsadc", "clk_saradc", "clk_spi0", "clk_spi1", "clk_spi2", "clk_uart4_div", "uart4_frac", "reserved", "reserved"; rockchip,suspend-clkgating-setting=<0x000f 0x000f>; #clock-cells = <1>; }; clk_gates3: gate-clk@016c { compatible = "rockchip,rk3188-gate-clk"; reg = <0x016c 0x4>; clocks = <&aclk_vio0>, <&dclk_lcdc0>, <&aclk_vio1>, <&dclk_lcdc1>, <&clk_rga>, <&aclk_rga>, <&ehci1phy_480m>, <&clk_cif_pll>, <&dummy>, <&clk_vepu>, <&dummy>, <&clk_vdpu>, <&clk_edp_24m>, <&clk_edp>, <&clk_isp>, <&clk_isp_jpe>; clock-output-names = "aclk_vio0", "dclk_lcdc0", "aclk_vio1", "dclk_lcdc1", "clk_rga", "aclk_rga", "ehci1phy_480m", "clk_cif_pll", /*Not use hclk_vpu_gate tmp, fixme*/ "reserved", "clk_vepu", "reserved", "clk_vdpu", "clk_edp_24m", "clk_edp", "clk_isp", "clk_isp_jpe"; rockchip,suspend-clkgating-setting=<0x0000 0x0000>; #clock-cells = <1>; }; clk_gates4: gate-clk@0170 { compatible = "rockchip,rk3188-gate-clk"; reg = <0x0170 0x4>; clocks = <&clk_i2s_out>, <&clk_i2s_pll>, <&i2s_frac>, <&clk_i2s>, <&spdif_div>, <&spdif_frac>, <&clk_spdif>, <&spdif_8ch_div>, <&spdif_8ch_frac>, <&clk_spdif_8ch>, <&clk_tsp>, <&clk_tspout>, <&clk_ddr>, <&clk_ddr>, <&jtag_clkin>, <&dummy>; clock-output-names = "clk_i2s_out", "clk_i2s_pll", "i2s_frac", "clk_i2s", "spdif_div", "spdif_frac", "clk_spdif", "spdif_8ch_div", "spdif_8ch_frac", "clk_spdif_8ch", "clk_tsp", "clk_tspout", /* Not use these ddr gates */ "reserved", "reserved", /*"g_clk_ddrphy0", "g_clk_ddrphy1",*/ "clk_jtag", "reserved"; /*"testclk_gate_en";*/ rockchip,suspend-clkgating-setting=<0xf000 0xf000>; #clock-cells = <1>; }; clk_gates5: gate-clk@0174 { compatible = "rockchip,rk3188-gate-clk"; reg = <0x0174 0x4>; clocks = <&clk_mac>, <&clk_mac>, <&clk_mac>, <&clk_mac>, <&clk_crypto>, <&clk_nandc0>, <&clk_nandc1>, <&clk_gpu>, <&pclk_pd_pmu>, <&xin24m>, <&xin24m>, <&xin32k>, <&xin24m>, <&xin24m>, <&usbphy_480m>, <&xin24m>; clock-output-names = "g_clk_mac_rx", "g_clk_mac_tx", "g_clk_mac_ref", "g_mac_refout", "clk_crypto", "clk_nandc0", "clk_nandc1", "clk_gpu", "pclk_pd_pmu", "g_clk_pvtm_core", "g_clk_pvtm_gpu", "g_hdmi_cec_clk", "g_hdmi_hdcp_clk", "g_ps2c_clk", "usbphy_480m", "g_mipidsi_24m"; rockchip,suspend-clkgating-setting=<0x0100 0x0100>; #clock-cells = <1>; }; clk_gates6: gate-clk@0178 { compatible = "rockchip,rk3188-gate-clk"; reg = <0x0178 0x4>; clocks = <&hclk_peri>, <&pclk_peri>, <&aclk_peri>, <&aclk_peri>, <&pclk_peri>, <&pclk_peri>, <&pclk_peri>, <&pclk_peri>, <&pclk_peri>, <&pclk_peri>, <&dummy>, <&pclk_peri>, <&pclk_peri>, <&pclk_peri>, <&pclk_peri>, <&pclk_peri>; clock-output-names = "g_hp_matrix", "g_pp_axi_matrix", "g_ap_axi_matrix", "g_aclk_dmac2", "g_pclk_spi0", "g_pclk_spi1", "g_pclk_spi2", "g_pclk_ps2c", "g_pclk_uart0", "g_pclk_uart1", "reserved", "g_pclk_uart3", "g_pclk_uart4", "g_pclk_i2c1", "g_pclk_i2c3", "g_pclk_i2c4"; rockchip,suspend-clkgating-setting=<0x0003 0x0003>; #clock-cells = <1>; }; clk_gates7: gate-clk@017c { compatible = "rockchip,rk3188-gate-clk"; reg = <0x017c 0x4>; clocks = <&pclk_peri>, <&pclk_peri>, <&pclk_peri>, <&pclk_peri>, <&hclk_peri>, <&hclk_peri>, <&hclk_peri>, <&hclk_peri>, <&hclk_peri>, <&hclk_peri>, <&hclk_peri>, <&aclk_peri>, <&hclk_peri>, <&hclk_peri>, <&hclk_peri>, <&hclk_peri>; clock-output-names = "g_pclk_i2c5", "g_pclk_saradc", "g_pclk_tsadc", "g_pclk_sim", "g_hclk_otg0", "g_pmu_hclk_otg0", "g_hclk_host0", "g_hclk_host1", "g_hclk_ehci1", "g_hclk_usb_peri", "g_hp_ahb_arbi", "g_aclk_peri_niu", "g_h_emem_peri", "g_hclk_mem_peri", "g_hclk_nandc0", "g_hclk_nandc1"; rockchip,suspend-clkgating-setting=<0x0c00 0xc000>; #clock-cells = <1>; }; clk_gates8: gate-clk@0180 { compatible = "rockchip,rk3188-gate-clk"; reg = <0x0180 0x4>; clocks = <&aclk_peri>, <&pclk_peri>, <&aclk_peri>, <&hclk_peri>, <&hclk_peri>, <&hclk_peri>, <&hclk_peri>, <&hclk_peri>, <&hclk_peri>, <&hsadc_0_tsp>, <&hsadc_1_tsp>, <&io_27m_in>, <&aclk_peri>, <&dummy>, <&dummy>, <&dummy>; clock-output-names = "g_aclk_gmac", "g_pclk_gmac", "g_hclk_gps", "g_hclk_sdmmc", "g_hclk_sdio0", "g_hclk_sdio1", "g_hclk_emmc", "g_hclk_hsadc", "g_hclk_tsp", "g_hsadc_0_tsp", "g_hsadc_1_tsp", "g_clk_27m_tsp", "g_aclk_peri_mmu", "reserved", "reserved", "reserved"; rockchip,suspend-clkgating-setting=<0x0000 0x0000>; #clock-cells = <1>; }; clk_gates9: gate-clk@0184 { compatible = "rockchip,rk3188-gate-clk"; reg = <0x0184 0x4>; clocks = <&dummy>, <&dummy>, <&dummy>, <&dummy>, <&dummy>, <&dummy>, <&dummy>, <&dummy>, <&dummy>, <&dummy>, <&dummy>, <&dummy>, <&dummy>, <&dummy>, <&dummy>, <&dummy>; clock-output-names = "reserved", "reserved", /*"aclk_video_gate_en", "hclk_video_clock_en",*/ "reserved", "reserved", "reserved", "reserved", "reserved", "reserved", "reserved", "reserved", "reserved", "reserved", "reserved", "reserved", "reserved", "reserved"; rockchip,suspend-clkgating-setting=<0x0 0x0>; #clock-cells = <1>; }; clk_gates10: gate-clk@0188 { compatible = "rockchip,rk3188-gate-clk"; reg = <0x0188 0x4>; clocks = <&pclk_bus>, <&pclk_bus>, <&pclk_bus>, <&pclk_bus>, <&aclk_bus>, <&aclk_bus>, <&aclk_bus>, <&aclk_bus>, <&hclk_bus>, <&hclk_bus>, <&hclk_bus>, <&hclk_bus>, <&aclk_bus>, <&aclk_bus>, <&pclk_bus>, <&pclk_bus>; clock-output-names = "g_pclk_pwm", "g_pclk_timer", "g_pclk_i2c0", "g_pclk_i2c2", "g_aclk_intmem", "g_clk_intmem0", "g_clk_intmem1", "g_clk_intmem2", "g_hclk_i2s", "g_hclk_rom", "g_hclk_spdif", "g_h_spdif_8ch", "g_aclk_dmac1", "g_aclk_strc_sys", "reserved", "reserved"; /*"g_p_ddrupctl0", "g_pclk_publ0";*/ //rockchip,suspend-clkgating-setting=<0xe2f1 0xe2f1>; // use sram mem no gating rockchip,suspend-clkgating-setting=<0xf2f1 0xf2f1>; // pwm logic vol #clock-cells = <1>; }; clk_gates11: gate-clk@018c { compatible = "rockchip,rk3188-gate-clk"; reg = <0x018c 0x4>; clocks = <&pclk_bus>, <&pclk_bus>, <&pclk_bus>, <&pclk_bus>, <&dummy>, <&dummy>, <&aclk_bus>, <&hclk_bus>, <&aclk_bus>, <&pclk_bus>, <&pclk_bus>, <&pclk_bus>, <&dummy>, <&dummy>, <&dummy>, <&dummy>; clock-output-names = "reserved", "reserved", /*"g_p_ddrupctl1", "g_pclk_publ1",*/ "g_p_efuse_1024", "g_pclk_tzpc", "reserved", "reserved", /*"g_nclk_ddrupctl0", "g_nclk_ddrupctl1"*/ "g_aclk_crypto", "g_hclk_crypto", "g_aclk_ccp", "g_pclk_uart2", "g_p_efuse_256", "g_pclk_rkpwm", "reserved", "reserved", "reserved", "reserved"; rockchip,suspend-clkgating-setting=<0x0033 0x0033>; #clock-cells = <1>; }; clk_gates12: gate-clk@0190 { compatible = "rockchip,rk3188-gate-clk"; reg = <0x0190 0x4>; clocks = <&clk_core0>, <&clk_core1>, <&clk_core2>, <&clk_core3>, <&clk_l2ram>, <&aclk_core_m0>, <&aclk_core_mp>, <&atclk_core>, <&pclk_dbg_src>, <&pclk_dbg_src>, <&pclk_dbg_src>, <&pclk_dbg_src>, <&dummy>, <&dummy>, <&dummy>, <&dummy>; clock-output-names = "clk_core0", "clk_core1", "clk_core2", "clk_core3", "clk_l2ram", "aclk_core_m0", "aclk_core_mp", "atclk_core", "pclk_dbg_src", "g_dbg_core_clk", "g_cs_dbg_clk", "g_pclk_core_niu", "reserved", "reserved", "reserved", "reserved"; rockchip,suspend-clkgating-setting=<0x0ff1 0x0ff1>; #clock-cells = <1>; }; clk_gates13: gate-clk@0194 { compatible = "rockchip,rk3188-gate-clk"; reg = <0x0194 0x4>; clocks = <&clk_sdmmc>, <&clk_sdio0>, <&clk_sdio1>, <&clk_emmc>, <&xin24m>, <&xin24m>, <&xin24m>, <&xin32k>, <&aclk_bus_src>, <&xin12m>, <&xin24m>, <&xin24m>, <&dummy>, <&aclk_hevc>, <&clk_hevc_cabac>, <&clk_hevc_core>; clock-output-names = "clk_sdmmc", "clk_sdio0", "clk_sdio1", "clk_emmc", "clk_otgphy0", "clk_otgphy1", "clk_otgphy2", "clk_otg_adp", "g_clk_c2c_host", "g_clk_ehci1_12m", "g_clk_lcdc_pwm0", "g_clk_lcdc_pwm1", "g_clk_wifi", "aclk_hevc", "clk_hevc_cabac", "clk_hevc_core"; rockchip,suspend-clkgating-setting=<0x0 0x0>; #clock-cells = <1>; }; clk_gates14: gate-clk@0198 { compatible = "rockchip,rk3188-gate-clk"; reg = <0x0198 0x4>; clocks = <&dummy>, <&pclk_pd_alive>, <&pclk_pd_alive>, <&pclk_pd_alive>, <&pclk_pd_alive>, <&pclk_pd_alive>, <&pclk_pd_alive>, <&pclk_pd_alive>, <&pclk_pd_alive>, <&dummy>, <&dummy>, <&pclk_pd_alive>, <&pclk_pd_alive>, <&dummy>, <&dummy>, <&dummy>; clock-output-names = "reserved", "g_pclk_gpio1", "g_pclk_gpio2", "g_pclk_gpio3", "g_pclk_gpio4", "g_pclk_gpio5", "g_pclk_gpio6", "g_pclk_gpio7", "g_pclk_gpio8", "reserved", "reserved", "g_pclk_grf", "g_p_alive_niu", "reserved", "reserved", "reserved"; //rockchip,suspend-clkgating-setting=<0xffff 0xffff>; rockchip,suspend-clkgating-setting=<0x19fe 0x19fe>; #clock-cells = <1>; }; clk_gates15: gate-clk@019c { compatible = "rockchip,rk3188-gate-clk"; reg = <0x019c 0x4>; clocks = <&aclk_rga>, <&hclk_vio>, <&clk_gates15 11>, <&hclk_vio>, <&dummy>, <&clk_gates15 11>, <&hclk_vio>, <&clk_gates15 12>, <&hclk_vio>, <&dummy>, <&dummy>, <&aclk_vio0>, <&aclk_vio1>, <&aclk_rga>, <&clk_gates15 11>, <&hclk_vio>; clock-output-names = "reserved", /*"g_aclk_rga"*/ "g_hclk_rga", "g_aclk_iep", "g_hclk_iep", "g_aclk_lcdc_iep", "g_aclk_lcdc0", "g_hclk_lcdc0", "g_aclk_lcdc1", "g_hclk_lcdc1", "reserved", /* "g_h_vio_ahb" */ "reserved",/*"g_hclk_vio_niu"*/ "g_aclk_vio0_niu", "g_aclk_vio1_niu", "reserved",/*"g_aclk_rga_niu"*/ "g_aclk_vip", "g_hclk_vip"; rockchip,suspend-clkgating-setting=<0x0 0x0>; #clock-cells = <1>; }; clk_gates16: gate-clk@01a0 { compatible = "rockchip,rk3188-gate-clk"; reg = <0x01a0 0x4>; clocks = <&pclkin_cif>, <&hclk_vio>, <&clk_gates15 12>, <&pclkin_isp>, <&hclk_vio>, <&hclk_vio>, <&hclk_vio>, <&hclk_vio>, <&hclk_vio>, <&hclk_vio>, <&dummy>, <&dummy>, <&dummy>, <&dummy>, <&dummy>, <&dummy>; clock-output-names = "g_pclkin_cif", "g_hclk_isp", "g_aclk_isp", "g_pclkin_isp", "g_p_mipi_dsi0", "g_p_mipi_dsi1", "g_p_mipi_csi", "g_pclk_lvds_phy", "g_pclk_edp_ctrl", "g_p_hdmi_ctrl", "reserved", "reserved", /* bit10:"g_hclk_vio2_h2p" bit11: "g_pclk_vio2_h2p" */ "reserved", "reserved", "reserved", "reserved"; rockchip,suspend-clkgating-setting=<0x0 0x0>; #clock-cells = <1>; }; clk_gates17: gate-clk@01a4 { compatible = "rockchip,rk3188-gate-clk"; reg = <0x01a4 0x4>; clocks = <&pclk_pd_pmu>, <&pclk_pd_pmu>, <&pclk_pd_pmu>, <&pclk_pd_pmu>, <&pclk_pd_pmu>, <&dummy>, <&dummy>, <&dummy>, <&dummy>, <&dummy>, <&dummy>, <&dummy>, <&dummy>, <&dummy>, <&dummy>, <&dummy>; clock-output-names = "g_pclk_pmu", "g_pclk_intmem1", "g_pclk_pmu_niu", "g_pclk_sgrf", "g_pclk_gpio0", "reserved", "reserved", "reserved", "reserved", "reserved", "reserved", "reserved", "reserved", "reserved", "reserved", "reserved"; rockchip,suspend-clkgating-setting=<0x01f 0x01f>; #clock-cells = <1>; }; clk_gates18: gate-clk@01a8 { compatible = "rockchip,rk3188-gate-clk"; reg = <0x01a8 0x4>; clocks = <&clk_gpu>, <&dummy>, <&dummy>, <&dummy>, <&dummy>, <&dummy>, <&dummy>, <&dummy>, <&dummy>, <&dummy>, <&dummy>, <&dummy>, <&dummy>, <&dummy>, <&dummy>, <&dummy>; clock-output-names = "reserved", /*"g_aclk_gpu",*/ "reserved", "reserved", "reserved", "reserved", "reserved", "reserved", "reserved", "reserved", "reserved", "reserved", "reserved", "reserved", "reserved", "reserved", "reserved"; rockchip,suspend-clkgating-setting=<0x0 0x0>; #clock-cells = <1>; }; }; }; }; };