关键词：rk3128-box-ns.dts ,linux_3.10,rockchip,dts
dts — rk3128-box-ns.dts
// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
#include "rk3128-box.dts"
/ {
chosen {
bootargs = "vmalloc=496M rockchip_jtag psci=enable";
};
fiq-debugger {
rockchip,irq-mode-enable = <1>;
status = "okay";
};
};
&clk_ddr_dvfs_table {
status = "disabled";
};
=> like ap6xxx, rk90x;
* rtkwifi ==> like rtl8188xx, rtl8723xx;
* esp8089 ==> esp8089;
* other ==> for other wifi;
*/
wifi_chip_type = "bcmwifi";
sdio_vref = <1800>; //1800mv or 3300mv
//keep_wifi_power_on;
//power_ctrl_by_pmu;
power_pmu_regulator = "act_ldo3";
power_pmu_enable_level = <1>; //1->HIGH, 0->LOW
//vref_ctrl_enable;
//vref_ctrl_gpio = <&gpio0 GPIO_A2 GPIO_ACTIVE_HIGH>;
vref_pmu_regulator = "act_ldo3";
vref_pmu_enable_level = <1>; //1->HIGH, 0->LOW
WIFI,poweren_gpio = <&gpio4 GPIO_D4 GPIO_ACTIVE_HIGH>;
WIFI,host_wake_irq = <&gpio4 GPIO_D6 GPIO_ACTIVE_HIGH>;
//WIFI,reset_gpio = <&gpio0 GPIO_A2 GPIO_ACTIVE_LOW>;
status = "okay";
};
wireless-bluetooth {
compatible = "bluetooth-platdata";
//wifi-bt-power-toggle;
uart_rts_gpios = <&gpio4 GPIO_C3 GPIO_ACTIVE_LOW>;
pinctrl-names = "default","rts_gpio";
pinctrl-0 = <&uart0_rts>;
pinctrl-1 = <&uart0_rts_gpio>;
BT,power_gpio = <&gpio4 GPIO_D3 GPIO_ACTIVE_HIGH>;
BT,reset_gpio = <&gpio4 GPIO_D5 GPIO_ACTIVE_HIGH>;
BT,wake_gpio = <&gpio4 GPIO_D2 GPIO_ACTIVE_HIGH>;
BT,wake_host_irq = <&gpio4 GPIO_D7 GPIO_ACTIVE_LOW>;
status = "okay";
};
hallsensor {
compatible = "hall_och165t";
type = <SENSOR_TYPE_HALL>;
irq-gpio = <&gpio0 GPIO_A6 IRQ_TYPE_EDGE_BOTH>;
};
backlight {
compatible = "pwm-backlight";
pwms = <&pwm0 0 25000>;
brightness-levels = <0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 101 102 103 104 105 106 107 108 109 110 111 112 113 114 115 116 117 118 119 120 121 122 123 124 125 126 127 128 129 130 131 132 133 134 135 136 137 138 139 140 141 142 143 144 145 146 147 148 149 150 151 152 153 154 155 156 157 158 159 160 161 162 163 164 165 166 167 168 169 170 171 172 173 174 175 176 177 178 179 180 181 182 183 184 185 186 187 188 189 190 191 192 193 194 195 196 197 198 199 200 201 202 203 204 205 206 207 208 209 210 211 212 213 214 215 216 217 218 219 220 221 222 223 224 225 226 227 228 229 230 231 232 233 234 235 236 237 238 239 240 241 242 243 244 245 246 247 248 249 250 251 252 253 254 255>;
default-brightness-level = <128>;
enable-gpios = <&gpio7 GPIO_A2 GPIO_ACTIVE_HIGH>;
};
pwm_regulator {
compatible = "rockchip_pwm_regulator";
pwms = <&pwm1 0 2000>;
rockchip,pwm_id= <1>;
rockchip,pwm_voltage_map= <925000 950000 975000 1000000 1025000 1050000 1075000 1100000 1125000 1150000 1175000 1200000 1225000 1250000 1275000 1300000 1325000 1350000 1375000 1400000>;
rockchip,pwm_voltage= <1000000>;
rockchip,pwm_min_voltage= <925000>;
rockchip,pwm_max_voltage= <1400000>;
rockchip,pwm_suspend_voltage= <950000>;
rockchip,pwm_coefficient= <475>;
regulators {
#address-cells = <1>;
#size-cells = <0>;
pwm_reg0: regulator@0 {
regulator-compatible = "pwm_dcdc1";
regulator-name= "vdd_logic";
regulator-min-microvolt = <925000>;
regulator-max-microvolt = <1400000>;
regulator-always-on;
regulator-boot-on;
};
};
};
codec_hdmi_i2s: codec-hdmi-i2s {
compatible = "hdmi-i2s";
};
codec_hdmi_spdif: codec-hdmi-spdif {
compatible = "hdmi-spdif";
};
rockchip-hdmi-i2s {
compatible = "rockchip-hdmi-i2s";
dais {
dai0 {
audio-codec = <&codec_hdmi_i2s>;
audio-controller = <&i2s>;
format = "i2s";
//continuous-clock;
//bitclock-inversion;
//frame-inversion;
//bitclock-master;
//frame-master;
};
};
};
rockchip-hdmi-spdif {
compatible = "rockchip-hdmi-spdif";
dais {
dai0 {
audio-codec = <&codec_hdmi_spdif>;
audio-controller = <&spdif>;
};
};
};
rockchip-rt5631 {
compatible = "rockchip-rt5631";
dais {
dai0 {
audio-codec = <&rt5631>;
audio-controller = <&i2s>;
format = "i2s";
//continuous-clock;
//bitclock-inversion;
//frame-inversion;
//bitclock-master;
//frame-master;
};
};
};
rockchip-rt3224 {
compatible = "rockchip-rt3261";
dais {
dai0 {
audio-codec = <&rt3261>;
audio-controller = <&i2s>;
format = "i2s";
//continuous-clock;
//bitclock-inversion;
//frame-inversion;
//bitclock-master;
//frame-master;
};
dai1 {
audio-codec = <&rt3261>;
audio-controller = <&i2s>;
format = "dsp_a";
//continuous-clock;
bitclock-inversion;
//frame-inversion;
//bitclock-master;
//frame-master;
};
};
};
usb_control {
compatible = "rockchip,rk3288-usb-control";
host_drv_gpio = <&gpio0 GPIO_B6 GPIO_ACTIVE_LOW>;
otg_drv_gpio = <&gpio0 GPIO_B4 GPIO_ACTIVE_LOW>;
rockchip,remote_wakeup;
rockchip,usb_irq_wakeup;
};
};
&gmac {
// power_ctl_by = "gpio"; //"gpio" "pmu"
power-gpio = <&gpio0 GPIO_A6 GPIO_ACTIVE_HIGH>;
// power-pmu = "act_ldo"
reset-gpio = <&gpio4 GPIO_A7 GPIO_ACTIVE_LOW>;
status = "disabled"; //if want to use gmac, please set "okay"
};
&pinctrl {
//used for init some gpio
init-gpios = <&gpio0 GPIO_A6 GPIO_ACTIVE_HIGH
/*&gpio0 GPIO_C2 GPIO_ACTIVE_HIGH */
/*&gpio7 GPIO_B7 GPIO_ACTIVE_LOW */>;
gpio0_gpio {
gpio0_c2: gpio0-c2 {
rockchip,pins = <GPIO0_C2>;
rockchip,pull = <VALUE_PULL_DOWN>;
};
//to add
};
gpio7_gpio {
gpio7_b7: gpio7-b7 {
rockchip,pins = <GPIO7_B7>;
rockchip,pull = <VALUE_PULL_UP>;
};
//to add
};
//could add other pinctrl definition such as gpio
};
&nandc0 {
status = "disabled"; // used nand set "disabled" ,used emmc set "okay"
};
&nandc1 {
status = "disabled"; // used nand set "disabled" ,used emmc set "okay"
};
&nandc0reg {
status = "okay"; // used nand set "disabled" ,used emmc set "okay"
};
&emmc {
clock-frequency = <100000000>;
clock-freq-min-max = <400000 100000000>;
supports-highspeed;
supports-emmc;
//supports-sd;
bootpart-no-access;
//supports-DDR_MODE; //you should set the two value in your project. only close in RK3288-SDK board.
//caps2-mmc-hs200;
ignore-pm-notify;
keep-power-in-suspend;
//poll-hw-reset
status = "okay";
};
&sdmmc {
clock-frequency = <50000000>;
clock-freq-min-max = <400000 50000000>;
supports-highspeed;
supports-sd;
broken-cd;
card-detect-delay = <200>;
ignore-pm-notify;
keep-power-in-suspend;
vmmc-supply = <&rk808_ldo5_reg>;
status = "okay";
};
&sdio {
clock-frequency = <50000000>;
clock-freq-min-max = <200000 50000000>;
supports-highspeed;
supports-sdio;
ignore-pm-notify;
keep-power-in-suspend;
//cap-sdio-irq;
status = "okay";
};
&spi0 {
status = "okay";
max-freq = <48000000>;
/*
spi_test@00 {
compatible = "rockchip,spi_test_bus0_cs0";
reg = <0>;
spi-max-frequency = <24000000>;
//spi-cpha;
//spi-cpol;
poll_mode = <0>;
type = <0>;
enable_dma = <0>;
};
spi_test@01 {
compatible = "rockchip,spi_test_bus0_cs1";
reg = <1>;
spi-max-frequency = <24000000>;
spi-cpha;
spi-cpol;
poll_mode = <0>;
type = <0>;
enable_dma = <0>;
};
*/
};
&spi1 {
status = "okay";
max-freq = <48000000>;
/*
spi_test@10 {
compatible = "rockchip,spi_test_bus1_cs0";
reg = <0>;
spi-max-frequency = <24000000>;
//spi-cpha;
//spi-cpol;
poll_mode = <0>;
type = <0>;
enable_dma = <0>;
};
*/
};
&spi2 {
status = "okay";
max-freq = <48000000>;
/*
spi_test@20 {
compatible = "rockchip,spi_test_bus2_cs0";
reg = <0>;
spi-max-frequency = <24000000>;
//spi-cpha;
//spi-cpol;
poll_mode = <0>;
type = <0>;
enable_dma = <0>;
};
spi_test@21 {
compatible = "rockchip,spi_test_bus2_cs1";
reg = <1>;
spi-max-frequency = <24000000>;
//spi-cpha;
//spi-cpol;
poll_mode = <0>;
type = <0>;
enable_dma = <0>;
};
*/
};
&uart_bt {
status = "okay";
dma-names = "!tx", "!rx";
pinctrl-0 = <&uart0_xfer &uart0_cts>;
};
&i2c0 {
status = "okay";
rk808: rk808@1b {
reg = <0x1b>;
status = "okay";
};
rk818: rk818@1c {
reg = <0x1c>;
status = "okay";
};
syr827: syr827@40 {
compatible = "silergy,syr82x";
reg = <0x40>;
status = "okay";
regulators {
#address-cells = <1>;
#size-cells = <0>;
syr827_dc1: regulator@0 {
reg = <0>;
regulator-compatible = "syr82x_dcdc1";
regulator-name = "vdd_arm";
regulator-min-microvolt = <712500>;
regulator-max-microvolt = <1500000>;
regulator-always-on;
regulator-boot-on;
regulator-initial-mode = <0x2>;
regulator-initial-state = <3>;
regulator-state-mem {
regulator-state-mode = <0x2>;
regulator-state-disabled;
regulator-state-uv = <900000>;
};
};
};
};
syr828: syr828@41 {
compatible = "silergy,syr82x";
reg = <0x41>;
status = "okay";
regulators {
#address-cells = <1>;
#size-cells = <0>;
syr828_dc1: regulator@0 {
reg = <0>;
regulator-compatible = "syr82x_dcdc1";
regulator-name = "vdd_gpu";
regulator-min-microvolt = <712500>;
regulator-max-microvolt = <1500000>;
regulator-always-on;
regulator-boot-on;
regulator-initial-mode = <0x2>;
regulator-initial-state = <3>;
regulator-state-mem {
regulator-state-mode = <0x2>;
regulator-state-enabled;
regulator-state-uv = <900000>;
};
};
};
};
act8846: act8846@5a {
reg = <0x5a>;
status = "okay";
};
ricoh619: ricoh619@32 {
reg = <0x32>;
status = "okay";
};
bq24296: bq24296@6b {
compatible = "ti,bq24296";
reg = <0x6b>;
gpios = <&gpio0 GPIO_A7 GPIO_ACTIVE_HIGH>,<&gpio0 GPIO_B0 GPIO_ACTIVE_HIGH>;
bq24296,chg_current = <1000 2000 3000>;
status = "okay";
};
bq27320: bq27320@55 {
compatible = "ti,bq27320";
reg = <0x55>;
/* gpios = <&gpio0 GPIO_A7 GPIO_ACTIVE_HIGH>; */
status = "okay";
};
CW2015@62 {
compatible = "cw201x";
reg = <0x62>;
dc_det_gpio = <&gpio0 GPIO_B0 GPIO_ACTIVE_LOW>;
bat_low_gpio = <&gpio0 GPIO_A7 GPIO_ACTIVE_LOW>;
chg_ok_gpio = <&gpio0 GPIO_B1 GPIO_ACTIVE_HIGH>;
bat_config_info = <0x15 0x42 0x60 0x59 0x52 0x58 0x4D 0x48 0x48 0x44 0x44 0x46 0x49 0x48 0x32
0x24 0x20 0x17 0x13 0x0F 0x19 0x3E 0x51 0x45 0x08 0x76 0x0B 0x85 0x0E 0x1C 0x2E 0x3E 0x4D 0x52 0x52
0x57 0x3D 0x1B 0x6A 0x2D 0x25 0x43 0x52 0x87 0x8F 0x91 0x94 0x52 0x82 0x8C 0x92 0x96 0xFF 0x7B 0xBB
0xCB 0x2F 0x7D 0x72 0xA5 0xB5 0xC1 0x46 0xAE>;
is_dc_charge = <1>;
is_usb_charge = <0>;
};
rtc@51 {
compatible = "rtc,hym8563";
reg = <0x51>;
irq_gpio = <&gpio0 GPIO_A4 IRQ_TYPE_EDGE_FALLING>;
};
};
&i2c1 {
status = "okay";
rtc@51 {
compatible = "nxp,pcf8563";
reg = <0x51>;
};
sensor@1d {
compatible = "gs_mma8452";
reg = <0x1d>;
type = <SENSOR_TYPE_ACCEL>;
irq-gpio = <&gpio8 GPIO_A0 IRQ_TYPE_EDGE_FALLING>;
irq_enable = <1>;
poll_delay_ms = <30>;
layout = <1>;
};
sensor@19 {
compatible = "gs_lis3dh";
reg = <0x19>;
type = <SENSOR_TYPE_ACCEL>;
irq-gpio = <&gpio0 GPIO_A0 IRQ_TYPE_LEVEL_LOW>;
irq_enable = <1>;
poll_delay_ms = <30>;
layout = <1>;
};
sensor@0d {
compatible = "ak8963";
reg = <0x0d>;
type = <SENSOR_TYPE_COMPASS>;
irq-gpio = <&gpio8 GPIO_A2 IRQ_TYPE_EDGE_RISING>;
irq_enable = <1>;
poll_delay_ms = <30>;
layout = <1>;
};
sensor@6b {
compatible = "l3g20d_gyro";
reg = <0x6b>;
type = <SENSOR_TYPE_GYROSCOPE>;
irq-gpio = <&gpio8 GPIO_A3 IRQ_TYPE_LEVEL_LOW>;
irq_enable = <1>;
poll_delay_ms = <30>;
layout = <1>;
};
sensor@10 {
compatible = "ls_cm3218";
reg = <0x10>;
type = <SENSOR_TYPE_LIGHT>;
irq-gpio = <&gpio8 GPIO_A3 IRQ_TYPE_EDGE_FALLING>;
irq_enable = <1>;
poll_delay_ms = <30>;
layout = <1>;
};
nfc-bcm2079x@76 {
compatible = "nfc-bcm2079x.ap6441";
reg = <0x76>;
en_gpio = <&gpio4 GPIO_D3 GPIO_ACTIVE_HIGH>;
wake_gpio = <&gpio5 GPIO_C0 GPIO_ACTIVE_HIGH>;
irq_gpio = <&gpio5 GPIO_B7 IRQ_TYPE_EDGE_RISING>;
status = "disabled";
};
nfc-bcm2079x@77 {
compatible = "nfc-bcm2079x.ap6493";
reg = <0x77>;
en_gpio = <&gpio4 GPIO_D3 GPIO_ACTIVE_HIGH>;
wake_gpio = <&gpio5 GPIO_C0 GPIO_ACTIVE_HIGH>;
irq_gpio = <&gpio5 GPIO_B7 IRQ_TYPE_EDGE_RISING>;
status = "disabled";
};
};
&i2c2 {
status = "okay";
rt5631: rt5631@1a {
compatible = "rt5631";
reg = <0x1a>;
};
es8323: es8323@10 {
compatible = "es8323";
reg = <0x10>;
};
rt3261: rt3261@1c {
compatible = "rt3261";
reg = <0x1c>;
// codec-en-gpio = <0>;//sdk default high level
spk-num= <2>;
modem-input-mode = <1>;
lout-to-modem_mode = <1>;
spk-amplify = <2>;
playback-if1-data_control = <0>;
playback-if2-data_control = <0>;
};
rt5616: rt5616@1b {
compatible = "rt5616";
reg = <0x1b>;
};
};
&i2c3 {
status = "okay";
};
&i2c4 {
status = "okay";
ts@55 {
compatible = "goodix,gt8xx";
reg = <0x55>;
touch-gpio = <&gpio7 GPIO_A6 IRQ_TYPE_LEVEL_LOW>;
reset-gpio = <&gpio7 GPIO_A5 GPIO_ACTIVE_LOW>;
//power-gpio = <&gpio0 GPIO_C5 GPIO_ACTIVE_LOW>;
max-x = <1280>;
max-y = <800>;
};
ts@01 {
compatible = "ct,vtl_ts";
reg = <0x01>;
screen_max_x = <2048>;
screen_max_y = <1536>;
irq_gpio_number = <&gpio7 GPIO_A6 IRQ_TYPE_LEVEL_LOW>;
rst_gpio_number = <&gpio7 GPIO_A5 GPIO_ACTIVE_HIGH>;
};
};
&i2c5 {
status = "disable";
};
&fb {
rockchip,disp-mode = <DUAL>;
rockchip,uboot-logo-on = <1>;
};
&rk_screen {
display-timings = <&disp_timings>;
};
/*lcdc0 as PRMRY(LCD),lcdc1 as EXTEND(HDMI)*/
&lcdc0 {
status = "okay";
rockchip,mirror = <NO_MIRROR>;
rockchip,cabc_mode = <0>;
power_ctr: power_ctr {
rockchip,debug = <0>;
lcd_en:lcd_en {
rockchip,power_type = <GPIO>;
gpios = <&gpio7 GPIO_A3 GPIO_ACTIVE_HIGH>;
rockchip,delay = <10>;
};
lcd_cs:lcd_cs {
rockchip,power_type = <GPIO>;
gpios = <&gpio7 GPIO_A4 GPIO_ACTIVE_HIGH>;
rockchip,delay = <10>;
};
/*lcd_rst:lcd_rst {
rockchip,power_type = <GPIO>;
gpios = <&gpio3 GPIO_D6 GPIO_ACTIVE_HIGH>;
rockchip,delay = <5>;
};*/
};
};
&lcdc1 {
status = "okay";
rockchip,mirror = <NO_MIRROR>;
};
&hdmi {
status = "okay";
rockchip,hdmi_video_source = <DISPLAY_SOURCE_LCDC1>;
};
&adc {
status = "okay";
rockchip_headset {
compatible = "rockchip_headset";
headset_gpio = <&gpio0 GPIO_C2 GPIO_ACTIVE_LOW>;
pinctrl-names = "default";
pinctrl-0 = <&gpio0_c2>;
io-channels = <&adc 2>;
/*
hook_gpio = ;
hook_down_type = ; //interrupt hook key down status
*/
};
key {
compatible = "rockchip,key";
io-channels = <&adc 1>;
vol-up-key {
linux,code = <115>;
label = "volume up";
rockchip,adc_value = <1>;
};
vol-down-key {
linux,code = <114>;
label = "volume down";
rockchip,adc_value = <170>;
};
power-key {
gpios = <&gpio0 GPIO_A5 GPIO_ACTIVE_LOW>;
linux,code = <116>;
label = "power";
gpio-key,wakeup;
};
menu-key {
linux,code = <59>;
label = "menu";
rockchip,adc_value = <355>;
};
home-key {
linux,code = <102>;
label = "home";
rockchip,adc_value = <746>;
};
back-key {
linux,code = <158>;
label = "back";
rockchip,adc_value = <560>;
};
camera-key {
linux,code = <212>;
label = "camera";
rockchip,adc_value = <450>;
};
};
};
&pwm0 {
status = "okay";
};
&pwm1 {
status = "okay";
};
&clk_core_dvfs_table {
operating-points = <
/* KHz uV */
126000 850000
216000 850000
312000 850000
408000 850000
600000 900000
696000 950000
816000 1000000
1008000 1050000
1200000 1100000
1416000 1200000
>;
status="okay";
};
&clk_gpu_dvfs_table {
operating-points = <
/* KHz uV */
100000 850000
200000 900000
300000 950000
420000 1050000
500000 1150000
>;
status="okay";
};
&clk_ddr_dvfs_table {
operating-points = <
/* KHz uV */
200000 950000
300000 950000
400000 1000000
533000 1050000
>;
freq-table = <
/*status freq(KHz)*/
SYS_STATUS_NORMAL 400000
SYS_STATUS_SUSPEND 200000
SYS_STATUS_VIDEO_1080P 240000
SYS_STATUS_VIDEO_4K 400000
SYS_STATUS_PERFORMANCE 528000
SYS_STATUS_DUALVIEW 400000
SYS_STATUS_BOOST 324000
SYS_STATUS_ISP 533000
>;
bd-freq-table = <
/* bandwidth freq */
5000 800000
3500 456000
2600 396000
2000 324000
>;
auto-freq-table = <
240000
324000
396000
528000
>;
auto-freq=<1>;
status="okay";
};
/include/ "act8846.dtsi"
&act8846 {
gpios =<&gpio7 GPIO_A1 GPIO_ACTIVE_LOW>,<&gpio0 GPIO_B2 GPIO_ACTIVE_HIGH>;
act8846,system-power-controller;
regulators {
dcdc1_reg: regulator@0{
regulator-name= "act_dcdc1";
regulator-min-microvolt = <1200000>;
regulator-max-microvolt = <1200000>;
regulator-always-on;
regulator-boot-on;
};
dcdc2_reg: regulator@1 {
regulator-name= "vccio";
regulator-min-microvolt = <3300000>;
regulator-max-microvolt = <3300000>;
regulator-initial-state = <3>;
regulator-state-mem {
regulator-state-enabled;
regulator-state-uv = <3300000>;
};
};
dcdc3_reg: regulator@2 {
regulator-name= "vdd_logic";
regulator-min-microvolt = <700000>;
regulator-max-microvolt = <1500000>;
regulator-initial-state = <3>;
regulator-state-mem {
regulator-state-enabled;
regulator-state-uv = <1200000>;
};
};
dcdc4_reg: regulator@3 {
regulator-name= "act_dcdc4";
regulator-min-microvolt = <2000000>;
regulator-max-microvolt = <2000000>;
regulator-initial-state = <3>;
regulator-state-mem {
regulator-state-enabled;
regulator-state-uv = <2000000>;
};
};
ldo1_reg: regulator@4 {
regulator-name= "vccio_sd";
regulator-min-microvolt = <1800000>;
regulator-max-microvolt = <3300000>;
};
ldo2_reg: regulator@5 {
regulator-name= "act_ldo2";
regulator-min-microvolt = <1000000>;
regulator-max-microvolt = <1000000>;
};
ldo3_reg: regulator@6 {
regulator-name= "act_ldo3";
regulator-min-microvolt = <3300000>;
regulator-max-microvolt = <3300000>;
};
ldo4_reg:regulator@7 {
regulator-name= "act_ldo4";
regulator-min-microvolt = <3300000>;
regulator-max-microvolt = <3300000>;
};
ldo5_reg: regulator@8 {
regulator-name= "act_ldo5";
regulator-min-microvolt = <3300000>;
regulator-max-microvolt = <3300000>;
};
ldo6_reg: regulator@9 {
regulator-name= "act_ldo6";
regulator-min-microvolt = <1000000>;
regulator-max-microvolt = <1000000>;
regulator-initial-state = <3>;
regulator-state-mem {
regulator-state-enabled;
};
};
ldo7_reg: regulator@10 {
regulator-name= "vcc_18";
regulator-min-microvolt = <1800000>;
regulator-max-microvolt = <1800000>;
regulator-initial-state = <3>;
regulator-state-mem {
regulator-state-enabled;
};
};
ldo8_reg: regulator@11 {
regulator-name= "act_ldo8";
regulator-min-microvolt = <1800000>;
regulator-max-microvolt = <1800000>;
};
};
};
/include/ "rk808.dtsi"
&rk808 {
gpios =<&gpio0 GPIO_A4 GPIO_ACTIVE_HIGH>,<&gpio0 GPIO_B3 GPIO_ACTIVE_LOW>;
rk808,system-power-controller;
regulators {
rk808_dcdc1_reg: regulator@0{
regulator-name= "vdd_arm";
regulator-min-microvolt = <700000>;
regulator-max-microvolt = <1500000>;
regulator-always-on;
regulator-boot-on;
regulator-initial-mode = <0x2>;
regulator-initial-state = <3>;
regulator-state-mem {
regulator-state-mode = <0x2>;
regulator-state-disabled;
regulator-state-uv = <900000>;
};
};
rk808_dcdc2_reg: regulator@1 {
regulator-name= "vdd_gpu";
regulator-min-microvolt = <700000>;
regulator-max-microvolt = <1500000>;
/*regulator-always-on;*/
/*regulator-boot-on;*/
regulator-initial-mode = <0x2>;
regulator-initial-state = <3>;
regulator-state-mem {
regulator-state-mode = <0x2>;
regulator-state-disabled;
regulator-state-uv = <900000>;
};
};
rk808_dcdc3_reg: regulator@2 {
regulator-name= "rk_dcdc3";
regulator-min-microvolt = <1200000>;
regulator-max-microvolt = <1200000>;
regulator-always-on;
regulator-boot-on;
regulator-initial-mode = <0x2>;
regulator-initial-state = <3>;
regulator-state-mem {
regulator-state-mode = <0x2>;
regulator-state-enabled;
regulator-state-uv = <1200000>;
};
};
rk808_dcdc4_reg: regulator@3 {
regulator-name= "vccio";
regulator-min-microvolt = <1800000>;
regulator-max-microvolt = <3300000>;
regulator-always-on;
regulator-boot-on;
regulator-initial-mode = <0x2>;
regulator-initial-state = <3>;
regulator-state-mem {
regulator-state-mode = <0x2>;
regulator-state-enabled;
regulator-state-uv = <2800000>;
};
};
rk808_ldo1_reg: regulator@4 {
regulator-name= "rk_ldo1";
regulator-min-microvolt = <3300000>;
regulator-max-microvolt = <3300000>;
regulator-always-on;
regulator-boot-on;
regulator-initial-state = <3>;
regulator-state-mem {
regulator-state-enabled;
regulator-state-uv = <3300000>;
};
};
rk808_ldo2_reg: regulator@5 {
regulator-name= "rk_ldo2";
regulator-min-microvolt = <3300000>;
regulator-max-microvolt = <3300000>;
regulator-always-on;
regulator-boot-on;
regulator-initial-state = <3>;
regulator-state-mem {
regulator-state-enabled;
regulator-state-uv = <3300000>;
};
};
rk808_ldo3_reg: regulator@6 {
regulator-name= "rk_ldo3";
regulator-min-microvolt = <1000000>;
regulator-max-microvolt = <1000000>;
regulator-always-on;
regulator-boot-on;
regulator-initial-state = <3>;
regulator-state-mem {
regulator-state-enabled;
regulator-state-uv = <1000000>;
};
};
rk808_ldo4_reg:regulator@7 {
regulator-name= "rk_ldo4";
regulator-min-microvolt = <1800000>;
regulator-max-microvolt = <1800000>;
regulator-always-on;
regulator-boot-on;
regulator-initial-state = <3>;
regulator-state-mem {
regulator-state-disabled;
regulator-state-uv = <1800000>;
};
};
rk808_ldo5_reg: regulator@8 {
regulator-name= "vcc_sd";
regulator-min-microvolt = <1800000>;
regulator-max-microvolt = <3300000>;
regulator-always-on;
regulator-boot-on;
regulator-initial-state = <3>;
regulator-state-mem {
regulator-state-enabled;
regulator-state-uv = <2800000>;
};
};
rk808_ldo6_reg: regulator@9 {
regulator-name= "rk_ldo6";
regulator-min-microvolt = <1000000>;
regulator-max-microvolt = <1000000>;
regulator-always-on;
regulator-boot-on;
regulator-initial-state = <3>;
regulator-state-mem {
regulator-state-disabled;
regulator-state-uv = <1000000>;
};
};
rk808_ldo7_reg: regulator@10 {
regulator-name= "rk_ldo7";
regulator-min-microvolt = <1800000>;
regulator-max-microvolt = <1800000>;
regulator-always-on;
regulator-boot-on;
regulator-initial-state = <3>;
regulator-state-mem {
regulator-state-enabled;
regulator-state-uv = <1800000>;
};
};
rk808_ldo8_reg: regulator@11 {
regulator-name= "rk_ldo8";
regulator-min-microvolt = <3300000>;
regulator-max-microvolt = <3300000>;
regulator-always-on;
regulator-boot-on;
regulator-initial-state = <3>;
regulator-state-mem {
regulator-state-enabled;
regulator-state-uv = <3300000>;
};
};
rk808_ldo9_reg: regulator@12 {
regulator-name= "rk_ldo9";
regulator-always-on;
regulator-boot-on;
regulator-initial-state = <3>;
regulator-state-mem {
regulator-state-enabled;
};
};
rk808_ldo10_reg: regulator@13 {
regulator-name= "rk_ldo10";
regulator-always-on;
regulator-boot-on;
regulator-initial-state = <3>;
regulator-state-mem {
regulator-state-disabled;
};
};
};
};
/include/ "ricoh619.dtsi"
&ricoh619 {
gpios =<&gpio0 GPIO_A4 GPIO_ACTIVE_HIGH>,<&gpio0 GPIO_B3 GPIO_ACTIVE_LOW>,<&gpio0 GPIO_B0 GPIO_ACTIVE_HIGH>;
ricoh619,system-power-controller;
regulators {
ricoh619_dcdc1_reg: regulator@0 {
regulator-name = "vccio";
regulator-min-microvolt = <3300000>;
regulator-max-microvolt = <3300000>;
regulator-initial-mode = <0x2>;
regulator-initial-state = <3>;
regulator-state-mem {
regulator-state-mode = <0x2>;
regulator-state-enabled;
regulator-state-uv = <2800000>;
};
};
ricoh619_dcdc2_reg: regulator@1 {
regulator-name = "ricoh619_dcdc2";
regulator-min-microvolt = <2000000>;
regulator-max-microvolt = <2000000>;
regulator-initial-mode = <0x2>;
regulator-initial-state = <3>;
regulator-state-mem {
regulator-state-mode = <0x2>;
regulator-state-enabled;
regulator-state-uv = <2000000>;
};
};
ricoh619_dcdc3_reg: regulator@2 {
regulator-name = "vcc_lcd";
regulator-min-microvolt = <3300000>;
regulator-max-microvolt = <3300000>;
regulator-initial-mode = <0x2>;
regulator-initial-state = <3>;
regulator-state-mem {
regulator-state-mode = <0x2>;
regulator-state-enabled;
regulator-state-uv = <3300000>;
};
};
ricoh619_dcdc4_reg: regulator@3 {
regulator-name = "vdd_logic";
regulator-min-microvolt = <700000>;
regulator-max-microvolt = <1500000>;
regulator-initial-mode = <0x2>;
regulator-initial-state = <3>;
regulator-state-mem {
regulator-state-mode = <0x2>;
regulator-state-enabled;
regulator-state-uv = <900000>;
};
};
ricoh619_dcdc5_reg: regulator@4 {
regulator-name = "vcc_ddr";
regulator-min-microvolt = <1200000>;
regulator-max-microvolt = <1200000>;
regulator-initial-mode = <0x2>;
regulator-initial-state = <3>;
regulator-state-mem {
regulator-state-mode = <0x2>;
regulator-state-enabled;
regulator-state-uv = <1200000>;
};
};
ricoh619_ldo1_reg: regulator@5 {
regulator-name = "vccio_pmu";
regulator-min-microvolt = <3300000>;
regulator-max-microvolt = <3300000>;
regulator-initial-state = <3>;
regulator-state-mem {
regulator-state-enabled;
regulator-state-uv = <3300000>;
};
};
ricoh619_ldo2_reg: regulator@6 {
regulator-name = "ricoh619_ldo2";
regulator-min-microvolt = <3300000>;
regulator-max-microvolt = <3300000>;
regulator-initial-state = <3>;
regulator-state-mem {
regulator-state-enabled;
regulator-state-uv = <3300000>;
};
};
ricoh619_ldo3_reg: regulator@7 {
regulator-name = "ricoh619_ldo3";
regulator-min-microvolt = <3300000>;
regulator-max-microvolt = <3300000>;
regulator-initial-state = <3>;
regulator-state-mem {
regulator-state-enabled;
regulator-state-uv = <3300000>;
};
};
ricoh619_ldo4_reg: regulator@8 {
regulator-name = "vcc_sd";
regulator-min-microvolt = <3300000>;
regulator-max-microvolt = <3300000>;
regulator-initial-state = <3>;
regulator-state-mem {
regulator-state-enabled;
regulator-state-uv = <3300000>;
};
};
ricoh619_ldo5_reg: regulator@9 {
regulator-name = "vcc_wl";
regulator-min-microvolt = <1800000>;
regulator-max-microvolt = <1800000>;
regulator-initial-state = <3>;
regulator-state-mem {
regulator-state-enabled;
regulator-state-uv = <1800000>;
};
};
ricoh619_ldo6_reg: regulator@10 {
regulator-name = "ricoh619_ldo6";
regulator-min-microvolt = <1800000>;
regulator-max-microvolt = <1800000>;
regulator-initial-state = <3>;
regulator-state-mem {
regulator-state-enabled;
regulator-state-uv = <1800000>;
};
};
ricoh619_ldo7_reg: regulator@11 {
regulator-name = "ricoh619_ldo7";
regulator-min-microvolt = <1000000>;
regulator-max-microvolt = <1000000>;
regulator-initial-state = <3>;
regulator-state-mem {
regulator-state-enabled;
regulator-state-uv = <1000000>;
};
};
ricoh619_ldo8_reg: regulator@12 {
regulator-name = "ricoh619_ldo8";
regulator-min-microvolt = <3300000>;
regulator-max-microvolt = <3300000>;
regulator-initial-state = <3>;
regulator-state-mem {
regulator-state-enabled;
regulator-state-uv = <3300000>;
};
};
ricoh619_ldo9_reg: regulator@13 {
regulator-name = "ricoh619_ldo9";
regulator-min-microvolt = <1000000>;
regulator-max-microvolt = <1000000>;
regulator-initial-state = <3>;
regulator-state-mem {
regulator-state-enabled;
regulator-state-uv = <1000000>;
};
};
ricoh619_ldo10_reg: regulator@14 {
regulator-name = "vcc_18";
regulator-min-microvolt = <1800000>;
regulator-max-microvolt = <1800000>;
regulator-initial-state = <3>;
regulator-state-mem {
regulator-state-enabled;
regulator-state-uv = <1800000>;
};
};
ricoh619_ldortc1_reg: regulator@15 {
regulator-name = "ricoh619_ldortc1";
regulator-min-microvolt = < 3300000>;
regulator-max-microvolt = <3300000>;
};
ricoh619_ldortc2_reg: regulator@16 {
regulator-name = "ricoh619_ldortc2";
regulator-min-microvolt = < 3300000>;
regulator-max-microvolt = <3300000>;
};
};
};
/include/ "rk818.dtsi"
&rk818 {
gpios =<&gpio0 GPIO_A4 GPIO_ACTIVE_HIGH>,<&gpio0 GPIO_B3 GPIO_ACTIVE_LOW>;
rk818,system-power-controller;
regulators {
rk818_dcdc1_reg: regulator@0{
regulator-name= "vdd_logic";
regulator-min-microvolt = <700000>;
regulator-max-microvolt = <1500000>;
regulator-initial-mode = <0x2>;
regulator-initial-state = <3>;
regulator-state-mem {
regulator-state-mode = <0x2>;
regulator-state-enabled;
regulator-state-uv = <900000>;
};
};
rk818_dcdc2_reg: regulator@1 {
regulator-name= "rk818_dcdc2";
regulator-min-microvolt = <1200000>;
regulator-max-microvolt = <1200000>;
regulator-initial-mode = <0x2>;
regulator-initial-state = <3>;
regulator-state-mem {
regulator-state-mode = <0x2>;
regulator-state-enabled;
regulator-state-uv = <1200000>;
};
};
rk818_dcdc3_reg: regulator@2 {
regulator-name= "rk818_dcdc3";
regulator-min-microvolt = <1200000>;
regulator-max-microvolt = <1200000>;
regulator-initial-mode = <0x2>;
regulator-initial-state = <3>;
regulator-state-mem {
regulator-state-mode = <0x2>;
regulator-state-enabled;
regulator-state-uv = <1200000>;
};
};
rk818_dcdc4_reg: regulator@3 {
regulator-name= "vccio";
regulator-min-microvolt = <1800000>;
regulator-max-microvolt = <3300000>;
regulator-initial-mode = <0x2>;
regulator-initial-state = <3>;
regulator-state-mem {
regulator-state-mode = <0x2>;
regulator-state-enabled;
regulator-state-uv = <2800000>;
};
};
rk818_ldo1_reg: regulator@4 {
regulator-name= "rk818_ldo1";
regulator-min-microvolt = <3300000>;
regulator-max-microvolt = <3300000>;
regulator-initial-state = <3>;
regulator-state-mem {
regulator-state-enabled;
regulator-state-uv = <3300000>;
};
};
rk818_ldo2_reg: regulator@5 {
regulator-name= "rk818_ldo2";
regulator-min-microvolt = <3300000>;
regulator-max-microvolt = <3300000>;
regulator-initial-state = <3>;
regulator-state-mem {
regulator-state-enabled;
regulator-state-uv = <3300000>;
};
};
rk818_ldo3_reg: regulator@6 {
regulator-name= "rk818_ldo3";
regulator-min-microvolt = <1000000>;
regulator-max-microvolt = <1000000>;
regulator-initial-state = <3>;
regulator-state-mem {
regulator-state-enabled;
regulator-state-uv = <1000000>;
};
};
rk818_ldo4_reg:regulator@7 {
regulator-name= "rk818_ldo4";
regulator-min-microvolt = <1800000>;
regulator-max-microvolt = <1800000>;
regulator-initial-state = <3>;
regulator-state-mem {
regulator-state-disabled;
regulator-state-uv = <1800000>;
};
};
rk818_ldo5_reg: regulator@8 {
regulator-name= "rk818_ldo5";
regulator-min-microvolt = <3300000>;
regulator-max-microvolt = <3300000>;
regulator-initial-state = <3>;
regulator-state-mem {
regulator-state-enabled;
regulator-state-uv = <3300000>;
};
};
rk818_ldo6_reg: regulator@9 {
regulator-name= "rk818_ldo6";
regulator-min-microvolt = <1000000>;
regulator-max-microvolt = <1000000>;
regulator-initial-state = <3>;
regulator-state-mem {
regulator-state-disabled;
regulator-state-uv = <1000000>;
};
};
rk818_ldo7_reg: regulator@10 {
regulator-name= "rk818_ldo7";
regulator-min-microvolt = <1800000>;
regulator-max-microvolt = <1800000>;
regulator-initial-state = <3>;
regulator-state-mem {
regulator-state-enabled;
regulator-state-uv = <1800000>;
};
};
rk818_ldo8_reg: regulator@11 {
regulator-name= "rk818_ldo8";
regulator-min-microvolt = <1800000>;
regulator-max-microvolt = <1800000>;
regulator-initial-state = <3>;
regulator-state-mem {
regulator-state-enabled;
regulator-state-uv = <1800000>;
};
};
rk818_ldo9_reg: regulator@12 {
regulator-name= "vcc_sd";
regulator-min-microvolt = <1800000>;
regulator-max-microvolt = <3300000>;
regulator-initial-state = <3>;
regulator-state-mem {
regulator-state-enabled;
regulator-state-uv = <3300000>;
};
};
rk818_ldo10_reg: regulator@13 {
regulator-name= "rk818_ldo10";
regulator-state-mem {
regulator-state-disabled;
};
};
};
battery {
ocv_table = <3350 3677 3693 3719 3752 3770 3775 3778 3785 3796 3812 3839 3881 3907 3933 3958 3978 4033 4087 4123 4174>;
design_capacity = <2100>;
design_qmax = <2200>;
max_overcharge = <100>;
bat_res = <80>;
max_input_currentmA = <2000>;
max_chrg_currentmA = <1800>;
max_charge_voltagemV = <4200>;
max_bat_voltagemV = <4200>;
sleep_enter_current = <300>;
sleep_exit_current = <300>;
power_off_thresd = <3400>;
chrg_diff_voltagemV = <0>;
virtual_power = <1>;
support_usb_adp = <0>;
support_dc_adp = <1>;
power_dc2otg = <0>;
dc_det_gpio = <&gpio0 GPIO_B0 GPIO_ACTIVE_LOW>;
};
};
&lcdc_vdd_domain {
regulator-name = "vcc30_lcd";
};
&dpio_vdd_domain{
regulator-name = "vcc18_cif";
};
&flash0_vdd_domain{
regulator-name = "vcc_flash";
};
&flash1_vdd_domain{
regulator-name = "vcc_flash";
};
&apio3_vdd_domain{
regulator-name = "vccio_wl";
};
&apio5_vdd_domain{
regulator-name = "vccio";
};
&apio4_vdd_domain{
regulator-name = "vccio";
};
&apio1_vdd_domain{
regulator-name = "vccio";
};
&apio2_vdd_domain{
regulator-name = "vccio";
};
&sdmmc0_vdd_domain{
regulator-name = "vcc_sd";
};
&dwc_control_usb {
usb_uart {
status = "disabled";
};
};
pull_none_drv_12ma>,
<1 20 RK_FUNC_1 &pcfg_pull_none_drv_12ma>,
<1 21 RK_FUNC_1 &pcfg_pull_none_drv_12ma>;
};
};
sdio {
sdio_clk: sdio-clk {
rockchip,pins = <3 0 RK_FUNC_1 &pcfg_pull_none_drv_12ma>;
};
sdio_cmd: sdio-cmd {
rockchip,pins = <3 1 RK_FUNC_1 &pcfg_pull_none_drv_12ma>;
};
sdio_bus4: sdio-bus4 {
rockchip,pins = <3 2 RK_FUNC_1 &pcfg_pull_none_drv_12ma>,
<3 3 RK_FUNC_1 &pcfg_pull_none_drv_12ma>,
<3 4 RK_FUNC_1 &pcfg_pull_none_drv_12ma>,
<3 5 RK_FUNC_1 &pcfg_pull_none_drv_12ma>;
};
};
emmc {
emmc_clk: emmc-clk {
rockchip,pins = <2 7 RK_FUNC_2 &pcfg_pull_none>;
};
emmc_cmd: emmc-cmd {
rockchip,pins = <1 22 RK_FUNC_2 &pcfg_pull_none>;
};
emmc_bus8: emmc-bus8 {
rockchip,pins = <1 24 RK_FUNC_2 &pcfg_pull_none>,
<1 25 RK_FUNC_2 &pcfg_pull_none>,
<1 26 RK_FUNC_2 &pcfg_pull_none>,
<1 27 RK_FUNC_2 &pcfg_pull_none>,
<1 28 RK_FUNC_2 &pcfg_pull_none>,
<1 29 RK_FUNC_2 &pcfg_pull_none>,
<1 30 RK_FUNC_2 &pcfg_pull_none>,
<1 31 RK_FUNC_2 &pcfg_pull_none>;
};
};
gmac {
rgmii_pins: rgmii-pins {
rockchip,pins = <2 14 RK_FUNC_1 &pcfg_pull_none>,
<2 12 RK_FUNC_1 &pcfg_pull_none>,
<2 25 RK_FUNC_1 &pcfg_pull_none>,
<2 19 RK_FUNC_1 &pcfg_pull_none_drv_12ma>,
<2 18 RK_FUNC_1 &pcfg_pull_none_drv_12ma>,
<2 22 RK_FUNC_1 &pcfg_pull_none_drv_12ma>,
<2 23 RK_FUNC_1 &pcfg_pull_none_drv_12ma>,
<2 9 RK_FUNC_1 &pcfg_pull_none_drv_12ma>,
<2 13 RK_FUNC_1 &pcfg_pull_none_drv_12ma>,
<2 17 RK_FUNC_1 &pcfg_pull_none>,
<2 16 RK_FUNC_1 &pcfg_pull_none>,
<2 21 RK_FUNC_2 &pcfg_pull_none>,
<2 20 RK_FUNC_2 &pcfg_pull_none>,
<2 11 RK_FUNC_1 &pcfg_pull_none>,
<2 8 RK_FUNC_1 &pcfg_pull_none>;
};
rmii_pins: rmii-pins {
rockchip,pins = <2 14 RK_FUNC_1 &pcfg_pull_none>,
<2 12 RK_FUNC_1 &pcfg_pull_none>,
<2 25 RK_FUNC_1 &pcfg_pull_none>,
<2 19 RK_FUNC_1 &pcfg_pull_none_drv_12ma>,
<2 18 RK_FUNC_1 &pcfg_pull_none_drv_12ma>,
<2 13 RK_FUNC_1 &pcfg_pull_none_drv_12ma>,
<2 17 RK_FUNC_1 &pcfg_pull_none>,
<2 16 RK_FUNC_1 &pcfg_pull_none>,
<2 8 RK_FUNC_1 &pcfg_pull_none>,
<2 15 RK_FUNC_1 &pcfg_pull_none>;
};
phy_pins: phy-pins {
rockchip,pins = <2 14 RK_FUNC_2 &pcfg_pull_none>,
<2 8 RK_FUNC_2 &pcfg_pull_none>;
};
};
hdmi {
hdmi_hpd: hdmi-hpd {
rockchip,pins = <0 15 RK_FUNC_1 &pcfg_pull_down>;
};
hdmii2c_xfer: hdmii2c-xfer {
rockchip,pins = <0 6 RK_FUNC_2 &pcfg_pull_none>,
<0 7 RK_FUNC_2 &pcfg_pull_none>;
};
hdmi_cec: hdmi-cec {
rockchip,pins = <0 RK_PC4 RK_FUNC_1 &pcfg_pull_none>;
};
};
i2c0 {
i2c0_xfer: i2c0-xfer {
rockchip,pins = <0 0 RK_FUNC_1 &pcfg_pull_none>,
<0 1 RK_FUNC_1 &pcfg_pull_none>;
};
};
i2c1 {
i2c1_xfer: i2c1-xfer {
rockchip,pins = <0 2 RK_FUNC_1 &pcfg_pull_none>,
<0 3 RK_FUNC_1 &pcfg_pull_none>;
};
};
i2c2 {
i2c2_xfer: i2c2-xfer {
rockchip,pins = <2 20 RK_FUNC_1 &pcfg_pull_none>,
<2 21 RK_FUNC_1 &pcfg_pull_none>;
};
};
i2c3 {
i2c3_xfer: i2c3-xfer {
rockchip,pins = <0 6 RK_FUNC_1 &pcfg_pull_none>,
<0 7 RK_FUNC_1 &pcfg_pull_none>;
};
};
tsp {
tsp_d0: tsp-d0 {
rockchip,pins = <2 19 RK_FUNC_2 &pcfg_pull_none>;
};
tsp_d1: tsp-d1 {
rockchip,pins = <2 18 RK_FUNC_2 &pcfg_pull_none>;
};
tsp_d2: tsp-d2 {
rockchip,pins = <2 17 RK_FUNC_2 &pcfg_pull_none>;
};
tsp_d3: tsp-d3 {
rockchip,pins = <2 16 RK_FUNC_2 &pcfg_pull_none>;
};
tsp_d4: tsp-d4 {
rockchip,pins = <2 25 RK_FUNC_2 &pcfg_pull_none>;
};
tsp_d5: tsp-d5 {
rockchip,pins = <2 24 RK_FUNC_2 &pcfg_pull_none>;
};
tsp_d6: tsp-d6 {
rockchip,pins = <2 15 RK_FUNC_2 &pcfg_pull_none>;
};
tsp_d7: tsp-d7 {
rockchip,pins = <2 13 RK_FUNC_2 &pcfg_pull_none>;
};
tsp_sync: tsp-sync {
rockchip,pins = <2 12 RK_FUNC_2 &pcfg_pull_none>;
};
tsp_clk: tsp-clk {
rockchip,pins = <2 11 RK_FUNC_2 &pcfg_pull_none>;
};
tsp_fail: tsp-fail {
rockchip,pins = <2 10 RK_FUNC_2 &pcfg_pull_none>;
};
tsp_valid: tsp-valid {
rockchip,pins = <2 9 RK_FUNC_2 &pcfg_pull_none>;
};
};
spi-0 {
spi0_clk: spi0-clk {
rockchip,pins = <0 9 RK_FUNC_2 &pcfg_pull_up>;
};
spi0_cs0: spi0-cs0 {
rockchip,pins = <0 14 RK_FUNC_2 &pcfg_pull_up>;
};
spi0_tx: spi0-tx {
rockchip,pins = <0 11 RK_FUNC_2 &pcfg_pull_up>;
};
spi0_rx: spi0-rx {
rockchip,pins = <0 13 RK_FUNC_2 &pcfg_pull_up>;
};
spi0_cs1: spi0-cs1 {
rockchip,pins = <1 12 RK_FUNC_1 &pcfg_pull_up>;
};
};
spi-1 {
spi1_clk: spi1-clk {
rockchip,pins = <0 23 RK_FUNC_2 &pcfg_pull_up>;
};
spi1_cs0: spi1-cs0 {
rockchip,pins = <2 2 RK_FUNC_2 &pcfg_pull_up>;
};
spi1_rx: spi1-rx {
rockchip,pins = <2 0 RK_FUNC_2 &pcfg_pull_up>;
};
spi1_tx: spi1-tx {
rockchip,pins = <2 1 RK_FUNC_2 &pcfg_pull_up>;
};
spi1_cs1: spi1-cs1 {
rockchip,pins = <2 3 RK_FUNC_2 &pcfg_pull_up>;
};
};
i2s1 {
i2s1_bus: i2s1-bus {
rockchip,pins = <0 8 RK_FUNC_1 &pcfg_pull_none>,
<0 9 RK_FUNC_1 &pcfg_pull_none>,
<0 11 RK_FUNC_1 &pcfg_pull_none>,
<0 12 RK_FUNC_1 &pcfg_pull_none>,
<0 13 RK_FUNC_1 &pcfg_pull_none>,
<0 14 RK_FUNC_1 &pcfg_pull_none>,
<1 2 RK_FUNC_2 &pcfg_pull_none>,
<1 4 RK_FUNC_2 &pcfg_pull_none>,
<1 5 RK_FUNC_2 &pcfg_pull_none>;
};
};
pwm0 {
pwm0_pin: pwm0-pin {
rockchip,pins = <3 21 RK_FUNC_1 &pcfg_pull_none>;
};
pwm0_pin_pull_down: pwm0-pin-pull-down {
rockchip,pins = <3 21 RK_FUNC_1 &pcfg_pull_down>;
};
};
pwm1 {
pwm1_pin: pwm1-pin {
rockchip,pins = <0 30 RK_FUNC_2 &pcfg_pull_none>;
};
pwm1_pin_pull_down: pwm1-pin-pull-down {
rockchip,pins = <0 30 RK_FUNC_2 &pcfg_pull_down>;
};
};
pwm2 {
pwm2_pin: pwm2-pin {
rockchip,pins = <1 12 RK_FUNC_2 &pcfg_pull_none>;
};
pwm2_pin_pull_down: pwm2-pin-pull-down {
rockchip,pins = <1 12 RK_FUNC_2 &pcfg_pull_down>;
};
};
pwm3 {
pwm3_pin: pwm3-pin {
rockchip,pins = <1 11 RK_FUNC_2 &pcfg_pull_none>;
};
pwm3_pin_pull_down: pwm3-pin-pull-down {
rockchip,pins = <1 11 RK_FUNC_2 &pcfg_pull_down>;
};
};
spdif {
spdif_tx: spdif-tx {
rockchip,pins = <3 31 RK_FUNC_2 &pcfg_pull_none>;
};
};
tsadc {
otp_gpio: otp-gpio {
rockchip,pins = <0 24 RK_FUNC_GPIO &pcfg_pull_none>;
};
otp_out: otp-out {
rockchip,pins = <0 24 RK_FUNC_2 &pcfg_pull_none>;
};
};
uart0 {
uart0_xfer: uart0-xfer {
rockchip,pins = <2 26 RK_FUNC_1 &pcfg_pull_none>,
<2 27 RK_FUNC_1 &pcfg_pull_none>;
};
uart0_cts: uart0-cts {
rockchip,pins = <2 29 RK_FUNC_1 &pcfg_pull_none>;
};
uart0_rts: uart0-rts {
rockchip,pins = <0 17 RK_FUNC_1 &pcfg_pull_none>;
};
};
uart1 {
uart1_xfer: uart1-xfer {
rockchip,pins = <1 9 RK_FUNC_1 &pcfg_pull_none>,
<1 10 RK_FUNC_1 &pcfg_pull_none>;
};
uart1_cts: uart1-cts {
rockchip,pins = <1 8 RK_FUNC_1 &pcfg_pull_none>;
};
uart1_rts: uart1-rts {
rockchip,pins = <1 11 RK_FUNC_1 &pcfg_pull_none>;
};
};
uart1-1 {
uart11_xfer: uart11-xfer {
rockchip,pins = <3 14 RK_FUNC_1 &pcfg_pull_up>,
<3 13 RK_FUNC_1 &pcfg_pull_none>;
};
uart11_cts: uart11-cts {
rockchip,pins = <3 7 RK_FUNC_1 &pcfg_pull_none>;
};
uart11_rts: uart11-rts {
rockchip,pins = <3 6 RK_FUNC_1 &pcfg_pull_none>;
};
uart11_rts_gpio: uart11-rts-gpio {
rockchip,pins = <3 6 RK_FUNC_GPIO &pcfg_pull_none>;
};
};
uart2 {
uart2_xfer: uart2-xfer {
rockchip,pins = <1 18 RK_FUNC_2 &pcfg_pull_up>,
<1 19 RK_FUNC_2 &pcfg_pull_none>;
};
uart2_cts: uart2-cts {
rockchip,pins = <0 25 RK_FUNC_1 &pcfg_pull_none>;
};
uart2_rts: uart2-rts {
rockchip,pins = <0 24 RK_FUNC_1 &pcfg_pull_none>;
};
};
uart2-1 {
uart21_xfer: uart21-xfer {
rockchip,pins = <1 10 RK_FUNC_2 &pcfg_pull_up>,
<1 9 RK_FUNC_2 &pcfg_pull_none>;
};
};
};
psci {
compatible = "arm,psci-1.0";
method = "smc";
};
rockchip_suspend: rockchip-suspend {
compatible = "rockchip,pm-rk322x";
status = "disabled";
rockchip,virtual-poweroff = <0>;
rockchip,sleep-mode-config = <
(0
|RKPM_CTR_GTCLKS
|RKPM_CTR_IDLESRAM_MD
)
>;
};
};
{
compatible = "rockchip,rk3188-mux-con";
rockchip,bits = <6 2>;
clocks = <&clk_cpll>, <&clk_gpll>, <&usbphy_480m>;
clock-output-names = "aclk_vio0";
#clock-cells = <0>;
#clock-init-cells = <1>;
};
aclk_vio1_div: aclk_vio1_div {
compatible = "rockchip,rk3188-div-con";
rockchip,bits = <8 5>;
clocks = <&aclk_vio1>;
clock-output-names = "aclk_vio1";
rockchip,div-type = <CLK_DIVIDER_PLUS_ONE>;
#clock-cells = <0>;
rockchip,clkops-idx =
<CLKOPS_RATE_MUX_DIV>;
rockchip,flags = <CLK_SET_RATE_NO_REPARENT>;
};
/* reg[13]: reserved */
aclk_vio1: aclk_vio1_mux {
compatible = "rockchip,rk3188-mux-con";
rockchip,bits = <14 2>;
clocks = <&clk_cpll>, <&clk_gpll>, <&usbphy_480m>;
clock-output-names = "aclk_vio1";
#clock-cells = <0>;
#clock-init-cells = <1>;
};
};
clk_sel_con32: sel-con@00e0 {
compatible = "rockchip,rk3188-selcon";
reg = <0x00e0 0x4>;
#address-cells = <1>;
#size-cells = <1>;
clk_vepu_div: clk_vepu_div {
compatible = "rockchip,rk3188-div-con";
rockchip,bits = <0 5>;
clocks = <&clk_vepu>;
clock-output-names = "clk_vepu";
rockchip,div-type = <CLK_DIVIDER_PLUS_ONE>;
#clock-cells = <0>;
rockchip,clkops-idx =
<CLKOPS_RATE_MUX_DIV>;
};
/* reg[5]: reserved */
clk_vepu: clk_vepu_mux {
compatible = "rockchip,rk3188-mux-con";
rockchip,bits = <6 2>;
clocks = <&dummy_cpll>, <&clk_gpll>, <&usbphy_480m>;
clock-output-names = "clk_vepu";
#clock-cells = <0>;
#clock-init-cells = <1>;
};
clk_vdpu_div: clk_vdpu_div {
compatible = "rockchip,rk3188-div-con";
rockchip,bits = <8 5>;
clocks = <&clk_vdpu>;
clock-output-names = "clk_vdpu";
rockchip,div-type = <CLK_DIVIDER_PLUS_ONE>;
#clock-cells = <0>;
rockchip,clkops-idx =
<CLKOPS_RATE_MUX_DIV>;
};
/* reg[13]: reserved */
clk_vdpu: clk_vdpu_mux {
compatible = "rockchip,rk3188-mux-con";
rockchip,bits = <14 2>;
clocks = <&dummy_cpll>, <&clk_gpll>, <&usbphy_480m>;
clock-output-names = "clk_vdpu";
#clock-cells = <0>;
#clock-init-cells = <1>;
};
};
clk_sel_con33: sel-con@00e4 {
compatible = "rockchip,rk3188-selcon";
reg = <0x00e4 0x4>;
#address-cells = <1>;
#size-cells = <1>;
pclk_pd_pmu: pclk_pd_pmu_div {
compatible = "rockchip,rk3188-div-con";
rockchip,bits = <0 5>;
clocks = <&clk_gpll>;
clock-output-names = "pclk_pd_pmu";
rockchip,div-type = <CLK_DIVIDER_PLUS_ONE>;
#clock-cells = <0>;
#clock-init-cells = <1>;
};
/* reg[7:5]: reserved */
pclk_pd_alive: pclk_pd_alive {
compatible = "rockchip,rk3188-div-con";
rockchip,bits = <8 5>;
clocks = <&clk_gpll>;
clock-output-names = "pclk_pd_alive";
rockchip,div-type = <CLK_DIVIDER_PLUS_ONE>;
#clock-cells = <0>;
#clock-init-cells = <1>;
};
/* reg[15:13]: reserved */
};
clk_sel_con34: sel-con@00e8 {
compatible = "rockchip,rk3188-selcon";
reg = <0x00e8 0x4>;
#address-cells = <1>;
#size-cells = <1>;
clk_gpu_div: clk_gpu_div {
compatible = "rockchip,rk3188-div-con";
rockchip,bits = <0 5>;
clocks = <&clk_gpu>;
clock-output-names = "clk_gpu";
rockchip,div-type = <CLK_DIVIDER_PLUS_ONE>;
#clock-cells = <0>;
rockchip,clkops-idx =
<CLKOPS_RATE_MUX_DIV>;
rockchip,flags = <CLK_SET_RATE_PARENT_IN_ORDER>;
};
/* reg[5]: reserved */
clk_gpu: clk_gpu_mux {
compatible = "rockchip,rk3188-mux-con";
rockchip,bits = <6 2>;
clocks = <&dummy_cpll>, <&clk_gpll>, <&usbphy_480m>, <&clk_npll>;
clock-output-names = "clk_gpu";
#clock-cells = <0>;
#clock-init-cells = <1>;
};
clk_sdio1_div: clk_sdio1_div {
compatible = "rockchip,rk3188-div-con";
rockchip,bits = <8 6>;
clocks = <&clk_sdio1>;
clock-output-names = "clk_sdio1";
rockchip,div-type = <CLK_DIVIDER_PLUS_ONE>;
#clock-cells = <0>;
rockchip,clkops-idx =
<CLKOPS_RATE_MUX_EVENDIV>;
};
clk_sdio1: clk_sdio1_mux {
compatible = "rockchip,rk3188-mux-con";
rockchip,bits = <14 2>;
clocks = <&dummy_cpll>, <&clk_gpll>, <&xin24m>;
clock-output-names = "clk_sdio1";
#clock-cells = <0>;
};
};
clk_sel_con35: sel-con@00ec {
compatible = "rockchip,rk3188-selcon";
reg = <0x00ec 0x4>;
#address-cells = <1>;
#size-cells = <1>;
clk_tsp_div: clk_tsp_div {
compatible = "rockchip,rk3188-div-con";
rockchip,bits = <0 5>;
clocks = <&clk_tsp>;
clock-output-names = "clk_tsp";
rockchip,div-type = <CLK_DIVIDER_PLUS_ONE>;
#clock-cells = <0>;
rockchip,clkops-idx =
<CLKOPS_RATE_MUX_DIV>;
};
/* reg[5]: reserved */
clk_tsp: clk_tsp_mux {
compatible = "rockchip,rk3188-mux-con";
rockchip,bits = <6 2>;
clocks = <&dummy_cpll>, <&clk_gpll>, <&clk_npll>;
clock-output-names = "clk_tsp";
#clock-cells = <0>;
#clock-init-cells = <1>;
};
clk_tspout_div: clk_tspout_div {
compatible = "rockchip,rk3188-div-con";
rockchip,bits = <8 5>;
clocks = <&clk_tspout>;
clock-output-names = "clk_tspout";
rockchip,div-type = <CLK_DIVIDER_PLUS_ONE>;
#clock-cells = <0>;
rockchip,clkops-idx =
<CLKOPS_RATE_MUX_DIV>;
};
/* reg[13]: reserved */
clk_tspout: clk_tspout_mux {
compatible = "rockchip,rk3188-mux-con";
rockchip,bits = <14 2>;
clocks = <&dummy_cpll>, <&clk_gpll>, <&clk_npll>, <&io_27m_in>;
clock-output-names = "clk_tspout";
#clock-cells = <0>;
#clock-init-cells = <1>;
};
};
clk_sel_con36: sel-con@00f0 {
compatible = "rockchip,rk3188-selcon";
reg = <0x00f0 0x4>;
#address-cells = <1>;
#size-cells = <1>;
clk_core0: clk_core0_div {
compatible = "rockchip,rk3188-div-con";
rockchip,bits = <0 3>;
clocks = <&clk_core>;
clock-output-names = "clk_core0";
rockchip,div-type = <CLK_DIVIDER_PLUS_ONE>;
#clock-cells = <0>;
rockchip,clkops-idx = <CLKOPS_RATE_CORE_CHILD>;
};
/* reg[3]: reserved */
clk_core1: clk_core1_div {
compatible = "rockchip,rk3188-div-con";
rockchip,bits = <4 3>;
clocks = <&clk_core>;
clock-output-names = "clk_core1";
rockchip,div-type = <CLK_DIVIDER_PLUS_ONE>;
#clock-cells = <0>;
rockchip,clkops-idx = <CLKOPS_RATE_CORE_CHILD>;
};
/* reg[7]: reserved */
clk_core2: clk_core2_div {
compatible = "rockchip,rk3188-div-con";
rockchip,bits = <8 3>;
clocks = <&clk_core>;
clock-output-names = "clk_core2";
rockchip,div-type = <CLK_DIVIDER_PLUS_ONE>;
#clock-cells = <0>;
rockchip,clkops-idx = <CLKOPS_RATE_CORE_CHILD>;
};
/* reg[11]: reserved */
clk_core3: clk_core3_div {
compatible = "rockchip,rk3188-div-con";
rockchip,bits = <12 3>;
clocks = <&clk_core>;
clock-output-names = "clk_core3";
rockchip,div-type = <CLK_DIVIDER_PLUS_ONE>;
#clock-cells = <0>;
rockchip,clkops-idx = <CLKOPS_RATE_CORE_CHILD>;
};
/* reg[15]: reserved */
};
clk_sel_con37: sel-con@00f4 {
compatible = "rockchip,rk3188-selcon";
reg = <0x00f4 0x4>;
#address-cells = <1>;
#size-cells = <1>;
clk_l2ram: clk_l2ram_div {
compatible = "rockchip,rk3188-div-con";
rockchip,bits = <0 3>;
clocks = <&clk_core>;
clock-output-names = "clk_l2ram";
rockchip,div-type = <CLK_DIVIDER_PLUS_ONE>;
#clock-cells = <0>;
rockchip,clkops-idx = <CLKOPS_RATE_CORE_CHILD>;
};
/* reg[3]: reserved */
atclk_core: atclk_core_div {
compatible = "rockchip,rk3188-div-con";
rockchip,bits = <4 5>;
clocks = <&clk_core>;
clock-output-names = "atclk_core";
rockchip,div-type = <CLK_DIVIDER_PLUS_ONE>;
#clock-cells = <0>;
rockchip,clkops-idx = <CLKOPS_RATE_CORE_CHILD>;
};
pclk_dbg_src: pclk_core_dbg_div {
compatible = "rockchip,rk3188-div-con";
rockchip,bits = <9 5>;
clocks = <&clk_core>;
clock-output-names = "pclk_dbg_src";
rockchip,div-type = <CLK_DIVIDER_PLUS_ONE>;
#clock-cells = <0>;
rockchip,clkops-idx = <CLKOPS_RATE_CORE_CHILD>;
};
/* reg[15:14]: reserved */
};
clk_sel_con38: sel-con@00f8 {
compatible = "rockchip,rk3188-selcon";
reg = <0x00f8 0x4>;
#address-cells = <1>;
#size-cells = <1>;
clk_nandc0_div: clk_nandc0_div {
compatible = "rockchip,rk3188-div-con";
rockchip,bits = <0 5>;
clocks = <&clk_nandc0>;
clock-output-names = "clk_nandc0";
rockchip,div-type = <CLK_DIVIDER_PLUS_ONE>;
#clock-cells = <0>;
rockchip,clkops-idx =
<CLKOPS_RATE_MUX_DIV>;
};
/* reg[6:5]: reserved */
clk_nandc0: clk_nandc0_mux {
compatible = "rockchip,rk3188-mux-con";
rockchip,bits = <7 1>;
clocks = <&dummy_cpll>, <&clk_gpll>;
clock-output-names = "clk_nandc0";
#clock-cells = <0>;
};
clk_nandc1_div: clk_nandc1_div {
compatible = "rockchip,rk3188-div-con";
rockchip,bits = <8 5>;
clocks = <&clk_nandc1>;
clock-output-names = "clk_nandc1";
rockchip,div-type = <CLK_DIVIDER_PLUS_ONE>;
#clock-cells = <0>;
rockchip,clkops-idx =
<CLKOPS_RATE_MUX_DIV>;
};
/* reg[14:13]: reserved */
clk_nandc1: clk_nandc1_mux {
compatible = "rockchip,rk3188-mux-con";
rockchip,bits = <15 1>;
clocks = <&dummy_cpll>, <&clk_gpll>;
clock-output-names = "clk_nandc1";
#clock-cells = <0>;
};
};
clk_sel_con39: sel-con@00fc {
compatible = "rockchip,rk3188-selcon";
reg = <0x00fc 0x4>;
#address-cells = <1>;
#size-cells = <1>;
clk_spi2_div: clk_spi2_div {
compatible = "rockchip,rk3188-div-con";
rockchip,bits = <0 7>;
clocks = <&clk_spi2>;
clock-output-names = "clk_spi2";
rockchip,div-type = <CLK_DIVIDER_PLUS_ONE>;
#clock-cells = <0>;
rockchip,clkops-idx =
<CLKOPS_RATE_MUX_DIV>;
};
clk_spi2: clk_spi2_mux {
compatible = "rockchip,rk3188-mux-con";
rockchip,bits = <7 1>;
clocks = <&dummy_cpll>, <&clk_gpll>;
clock-output-names = "clk_spi2";
#clock-cells = <0>;
};
aclk_hevc_div: aclk_hevc_div {
compatible = "rockchip,rk3188-div-con";
rockchip,bits = <8 5>;
clocks = <&aclk_hevc>;
clock-output-names = "aclk_hevc";
rockchip,div-type = <CLK_DIVIDER_PLUS_ONE>;
#clock-cells = <0>;
rockchip,clkops-idx =
<CLKOPS_RATE_MUX_DIV>;
rockchip,flags = <CLK_SET_RATE_PARENT_IN_ORDER>;
};
/* reg[13]: reserved */
aclk_hevc: aclk_hevc_mux {
compatible = "rockchip,rk3188-mux-con";
rockchip,bits = <14 2>;
clocks = <&dummy_cpll>, <&clk_gpll>, <&clk_npll>;
clock-output-names = "aclk_hevc";
#clock-cells = <0>;
#clock-init-cells = <1>;
};
};
clk_sel_con40: sel-con@0100 {
compatible = "rockchip,rk3188-selcon";
reg = <0x0100 0x4>;
#address-cells = <1>;
#size-cells = <1>;
spdif_8ch_div: spdif_8ch_div {
compatible = "rockchip,rk3188-div-con";
rockchip,bits = <0 7>;
clocks = <&clk_spdif_pll>;
clock-output-names = "spdif_8ch_div";
rockchip,div-type = <CLK_DIVIDER_PLUS_ONE>;
#clock-cells = <0>;
};
/* reg[7]: reserved */
clk_spdif_8ch: spdif_8ch_clk_mux {
compatible = "rockchip,rk3188-mux-con";
rockchip,bits = <8 2>;
clocks = <&spdif_8ch_div>, <&spdif_8ch_frac>, <&xin12m>;
clock-output-names = "clk_spdif_8ch";
#clock-cells = <0>;
rockchip,clkops-idx =
<CLKOPS_RATE_RK3288_I2S>;
rockchip,flags = <CLK_SET_RATE_PARENT>;
};
/* reg[11:10]: reserved */
hclk_hevc: hclk_hevc_div {
compatible = "rockchip,rk3188-div-con";
rockchip,bits = <12 2>;
clocks = <&aclk_hevc>;
clock-output-names = "hclk_hevc";
rockchip,div-type = <CLK_DIVIDER_PLUS_ONE>;
#clock-cells = <0>;
#clock-init-cells = <1>;
};
/* reg[15:14]: reserved */
};
clk_sel_con41: sel-con@0104 {
compatible = "rockchip,rk3188-selcon";
reg = <0x0104 0x4>;
#address-cells = <1>;
#size-cells = <1>;
spdif_8ch_frac: spdif_8ch_frac {
compatible = "rockchip,rk3188-frac-con";
clocks = <&spdif_8ch_div>;
clock-output-names = "spdif_8ch_frac";
/* numerator denominator */
rockchip,bits = <0 32>;
rockchip,clkops-idx =
<CLKOPS_RATE_FRAC>;
#clock-cells = <0>;
};
};
clk_sel_con42: sel-con@0108 {
compatible = "rockchip,rk3188-selcon";
reg = <0x0108 0x4>;
#address-cells = <1>;
#size-cells = <1>;
clk_hevc_cabac_div: clk_hevc_cabac_div {
compatible = "rockchip,rk3188-div-con";
rockchip,bits = <0 5>;
clocks = <&clk_hevc_cabac>;
clock-output-names = "clk_hevc_cabac";
rockchip,div-type = <CLK_DIVIDER_PLUS_ONE>;
#clock-cells = <0>;
rockchip,clkops-idx =
<CLKOPS_RATE_MUX_DIV>;
rockchip,flags = <CLK_SET_RATE_PARENT_IN_ORDER>;
};
/* reg[5]: reserved */
clk_hevc_cabac: clk_hevc_cabac_mux {
compatible = "rockchip,rk3188-mux-con";
rockchip,bits = <6 2>;
clocks = <&dummy_cpll>, <&clk_gpll>, <&clk_npll>;
clock-output-names = "clk_hevc_cabac";
#clock-cells = <0>;
#clock-init-cells = <1>;
};
clk_hevc_core_div: clk_hevc_core_div {
compatible = "rockchip,rk3188-div-con";
rockchip,bits = <8 5>;
clocks = <&clk_hevc_core>;
clock-output-names = "clk_hevc_core";
rockchip,div-type = <CLK_DIVIDER_PLUS_ONE>;
#clock-cells = <0>;
rockchip,clkops-idx =
<CLKOPS_RATE_MUX_DIV>;
rockchip,flags = <CLK_SET_RATE_PARENT_IN_ORDER>;
};
/* reg[13]: reserved */
clk_hevc_core: clk_hevc_core_mux {
compatible = "rockchip,rk3188-mux-con";
rockchip,bits = <14 2>;
clocks = <&dummy_cpll>, <&clk_gpll>, <&clk_npll>;
clock-output-names = "clk_hevc_core";
#clock-cells = <0>;
#clock-init-cells = <1>;
};
};
};
/* Gate control regs */
clk_gate_cons {
compatible = "rockchip,rk-gate-cons";
#address-cells = <1>;
#size-cells = <1>;
ranges ;
clk_gates0: gate-clk@0160 {
compatible = "rockchip,rk3188-gate-clk";
reg = <0x0160 0x4>;
clocks =
<&dummy>, <&clk_apll>,
<&clk_gpll>, <&aclk_bus>,
<&hclk_bus>, <&pclk_bus>,
<&dummy>, <&aclk_bus>,
<&clk_dpll>, <&clk_gpll>,
<&clk_gpll>, <&clk_cpll>,
<&xin24m>, <&dummy>,
<&dummy>, <&dummy>;
clock-output-names =
"reserved", "reserved", /* do not use bit1 = "core_apll" */
"clk_arm_gpll", "g_aclk_bus",
"hclk_bus", "pclk_bus",
"reserved", "aclk_bus_2pmu",
"reserved", "reserved", /*"clk_ddr_dpll", "clk_ddr_gpll",*/
"reserved", "reserved", /*"clk_bus_gpll", "clk_bus_cpll",*/
"clk_acc_efuse", "reserved",
"reserved", "reserved";
rockchip,suspend-clkgating-setting=<0x0fff 0x0fff>;
#clock-cells = <1>;
};
clk_gates1: gate-clk@0164 {
compatible = "rockchip,rk3188-gate-clk";
reg = <0x0164 0x4>;
clocks =
<&xin24m>, <&xin24m>,
<&xin24m>, <&xin24m>,
<&xin24m>, <&xin24m>,
<&dummy>, <&dummy>,
<&clk_uart0_pll>, <&uart0_frac>,
<&clk_uart1_div>, <&uart1_frac>,
<&clk_uart2_div>, <&uart2_frac>,
<&clk_uart3_div>, <&uart3_frac>;
clock-output-names =
"clk_timer0", "clk_timer1",
"clk_timer2", "clk_timer3",
"clk_timer4", "clk_timer5",
"reserved", "reserved",
"clk_uart0_pll", "uart0_frac",
"clk_uart1_div", "uart1_frac",
"clk_uart2_div", "uart2_frac",
"clk_uart3_div", "uart3_frac";
rockchip,suspend-clkgating-setting=<0x0 0x0>;
#clock-cells = <1>;
};
clk_gates2: gate-clk@0168 {
compatible = "rockchip,rk3188-gate-clk";
reg = <0x0168 0x4>;
clocks =
<&aclk_peri>, <&aclk_peri>,
<&hclk_peri>, <&pclk_peri>,
<&dummy>, <&clk_mac_pll>,
<&clk_hsadc_pll>, <&clk_tsadc>,
<&clk_saradc>, <&clk_spi0>,
<&clk_spi1>, <&clk_spi2>,
<&clk_uart4_div>, <&uart4_frac>,
<&dummy>, <&dummy>;
clock-output-names =
"aclk_peri", "reserved", /*"g_aclk_periph",*/
"hclk_peri", "pclk_peri",
"reserved", "clk_mac_pll",
"clk_hsadc_pll", "clk_tsadc",
"clk_saradc", "clk_spi0",
"clk_spi1", "clk_spi2",
"clk_uart4_div", "uart4_frac",
"reserved", "reserved";
rockchip,suspend-clkgating-setting=<0x000f 0x000f>;
#clock-cells = <1>;
};
clk_gates3: gate-clk@016c {
compatible = "rockchip,rk3188-gate-clk";
reg = <0x016c 0x4>;
clocks =
<&aclk_vio0>, <&dclk_lcdc0>,
<&aclk_vio1>, <&dclk_lcdc1>,
<&clk_rga>, <&aclk_rga>,
<&ehci1phy_480m>, <&clk_cif_pll>,
<&dummy>, <&clk_vepu>,
<&dummy>, <&clk_vdpu>,
<&clk_edp_24m>, <&clk_edp>,
<&clk_isp>, <&clk_isp_jpe>;
clock-output-names =
"aclk_vio0", "dclk_lcdc0",
"aclk_vio1", "dclk_lcdc1",
"clk_rga", "aclk_rga",
"ehci1phy_480m", "clk_cif_pll",
/*Not use hclk_vpu_gate tmp, fixme*/
"reserved", "clk_vepu",
"reserved", "clk_vdpu",
"clk_edp_24m", "clk_edp",
"clk_isp", "clk_isp_jpe";
rockchip,suspend-clkgating-setting=<0x0000 0x0000>;
#clock-cells = <1>;
};
clk_gates4: gate-clk@0170 {
compatible = "rockchip,rk3188-gate-clk";
reg = <0x0170 0x4>;
clocks =
<&clk_i2s_out>, <&clk_i2s_pll>,
<&i2s_frac>, <&clk_i2s>,
<&spdif_div>, <&spdif_frac>,
<&clk_spdif>, <&spdif_8ch_div>,
<&spdif_8ch_frac>, <&clk_spdif_8ch>,
<&clk_tsp>, <&clk_tspout>,
<&clk_ddr>, <&clk_ddr>,
<&jtag_clkin>, <&dummy>;
clock-output-names =
"clk_i2s_out", "clk_i2s_pll",
"i2s_frac", "clk_i2s",
"spdif_div", "spdif_frac",
"clk_spdif", "spdif_8ch_div",
"spdif_8ch_frac", "clk_spdif_8ch",
"clk_tsp", "clk_tspout",
/* Not use these ddr gates */
"reserved", "reserved", /*"g_clk_ddrphy0", "g_clk_ddrphy1",*/
"clk_jtag", "reserved"; /*"testclk_gate_en";*/
rockchip,suspend-clkgating-setting=<0xf000 0xf000>;
#clock-cells = <1>;
};
clk_gates5: gate-clk@0174 {
compatible = "rockchip,rk3188-gate-clk";
reg = <0x0174 0x4>;
clocks =
<&clk_mac>, <&clk_mac>,
<&clk_mac>, <&clk_mac>,
<&clk_crypto>, <&clk_nandc0>,
<&clk_nandc1>, <&clk_gpu>,
<&pclk_pd_pmu>, <&xin24m>,
<&xin24m>, <&xin32k>,
<&xin24m>, <&xin24m>,
<&usbphy_480m>, <&xin24m>;
clock-output-names =
"g_clk_mac_rx", "g_clk_mac_tx",
"g_clk_mac_ref", "g_mac_refout",
"clk_crypto", "clk_nandc0",
"clk_nandc1", "clk_gpu",
"pclk_pd_pmu", "g_clk_pvtm_core",
"g_clk_pvtm_gpu", "g_hdmi_cec_clk",
"g_hdmi_hdcp_clk", "g_ps2c_clk",
"usbphy_480m", "g_mipidsi_24m";
rockchip,suspend-clkgating-setting=<0x0100 0x0100>;
#clock-cells = <1>;
};
clk_gates6: gate-clk@0178 {
compatible = "rockchip,rk3188-gate-clk";
reg = <0x0178 0x4>;
clocks =
<&hclk_peri>, <&pclk_peri>,
<&aclk_peri>, <&aclk_peri>,
<&pclk_peri>, <&pclk_peri>,
<&pclk_peri>, <&pclk_peri>,
<&pclk_peri>, <&pclk_peri>,
<&dummy>, <&pclk_peri>,
<&pclk_peri>, <&pclk_peri>,
<&pclk_peri>, <&pclk_peri>;
clock-output-names =
"g_hp_matrix", "g_pp_axi_matrix",
"g_ap_axi_matrix", "g_aclk_dmac2",
"g_pclk_spi0", "g_pclk_spi1",
"g_pclk_spi2", "g_pclk_ps2c",
"g_pclk_uart0", "g_pclk_uart1",
"reserved", "g_pclk_uart3",
"g_pclk_uart4", "g_pclk_i2c1",
"g_pclk_i2c3", "g_pclk_i2c4";
rockchip,suspend-clkgating-setting=<0x0003 0x0003>;
#clock-cells = <1>;
};
clk_gates7: gate-clk@017c {
compatible = "rockchip,rk3188-gate-clk";
reg = <0x017c 0x4>;
clocks =
<&pclk_peri>, <&pclk_peri>,
<&pclk_peri>, <&pclk_peri>,
<&hclk_peri>, <&hclk_peri>,
<&hclk_peri>, <&hclk_peri>,
<&hclk_peri>, <&hclk_peri>,
<&hclk_peri>, <&aclk_peri>,
<&hclk_peri>, <&hclk_peri>,
<&hclk_peri>, <&hclk_peri>;
clock-output-names =
"g_pclk_i2c5", "g_pclk_saradc",
"g_pclk_tsadc", "g_pclk_sim",
"g_hclk_otg0", "g_pmu_hclk_otg0",
"g_hclk_host0", "g_hclk_host1",
"g_hclk_ehci1", "g_hclk_usb_peri",
"g_hp_ahb_arbi", "g_aclk_peri_niu",
"g_h_emem_peri", "g_hclk_mem_peri",
"g_hclk_nandc0", "g_hclk_nandc1";
rockchip,suspend-clkgating-setting=<0x0c00 0xc000>;
#clock-cells = <1>;
};
clk_gates8: gate-clk@0180 {
compatible = "rockchip,rk3188-gate-clk";
reg = <0x0180 0x4>;
clocks =
<&aclk_peri>, <&pclk_peri>,
<&aclk_peri>, <&hclk_peri>,
<&hclk_peri>, <&hclk_peri>,
<&hclk_peri>, <&hclk_peri>,
<&hclk_peri>, <&hsadc_0_tsp>,
<&hsadc_1_tsp>, <&io_27m_in>,
<&aclk_peri>, <&dummy>,
<&dummy>, <&dummy>;
clock-output-names =
"g_aclk_gmac", "g_pclk_gmac",
"g_hclk_gps", "g_hclk_sdmmc",
"g_hclk_sdio0", "g_hclk_sdio1",
"g_hclk_emmc", "g_hclk_hsadc",
"g_hclk_tsp", "g_hsadc_0_tsp",
"g_hsadc_1_tsp", "g_clk_27m_tsp",
"g_aclk_peri_mmu", "reserved",
"reserved", "reserved";
rockchip,suspend-clkgating-setting=<0x0000 0x0000>;
#clock-cells = <1>;
};
clk_gates9: gate-clk@0184 {
compatible = "rockchip,rk3188-gate-clk";
reg = <0x0184 0x4>;
clocks =
<&dummy>, <&dummy>,
<&dummy>, <&dummy>,
<&dummy>, <&dummy>,
<&dummy>, <&dummy>,
<&dummy>, <&dummy>,
<&dummy>, <&dummy>,
<&dummy>, <&dummy>,
<&dummy>, <&dummy>;
clock-output-names =
"reserved", "reserved", /*"aclk_video_gate_en", "hclk_video_clock_en",*/
"reserved", "reserved",
"reserved", "reserved",
"reserved", "reserved",
"reserved", "reserved",
"reserved", "reserved",
"reserved", "reserved",
"reserved", "reserved";
rockchip,suspend-clkgating-setting=<0x0 0x0>;
#clock-cells = <1>;
};
clk_gates10: gate-clk@0188 {
compatible = "rockchip,rk3188-gate-clk";
reg = <0x0188 0x4>;
clocks =
<&pclk_bus>, <&pclk_bus>,
<&pclk_bus>, <&pclk_bus>,
<&aclk_bus>, <&aclk_bus>,
<&aclk_bus>, <&aclk_bus>,
<&hclk_bus>, <&hclk_bus>,
<&hclk_bus>, <&hclk_bus>,
<&aclk_bus>, <&aclk_bus>,
<&pclk_bus>, <&pclk_bus>;
clock-output-names =
"g_pclk_pwm", "g_pclk_timer",
"g_pclk_i2c0", "g_pclk_i2c2",
"g_aclk_intmem", "g_clk_intmem0",
"g_clk_intmem1", "g_clk_intmem2",
"g_hclk_i2s", "g_hclk_rom",
"g_hclk_spdif", "g_h_spdif_8ch",
"g_aclk_dmac1", "g_aclk_strc_sys",
"reserved", "reserved"; /*"g_p_ddrupctl0", "g_pclk_publ0";*/
//rockchip,suspend-clkgating-setting=<0xe2f1 0xe2f1>; // use sram mem no gating
rockchip,suspend-clkgating-setting=<0xf2f1 0xf2f1>; // pwm logic vol
#clock-cells = <1>;
};
clk_gates11: gate-clk@018c {
compatible = "rockchip,rk3188-gate-clk";
reg = <0x018c 0x4>;
clocks =
<&pclk_bus>, <&pclk_bus>,
<&pclk_bus>, <&pclk_bus>,
<&dummy>, <&dummy>,
<&aclk_bus>, <&hclk_bus>,
<&aclk_bus>, <&pclk_bus>,
<&pclk_bus>, <&pclk_bus>,
<&dummy>, <&dummy>,
<&dummy>, <&dummy>;
clock-output-names =
"reserved", "reserved", /*"g_p_ddrupctl1", "g_pclk_publ1",*/
"g_p_efuse_1024", "g_pclk_tzpc",
"reserved", "reserved", /*"g_nclk_ddrupctl0", "g_nclk_ddrupctl1"*/
"g_aclk_crypto", "g_hclk_crypto",
"g_aclk_ccp", "g_pclk_uart2",
"g_p_efuse_256", "g_pclk_rkpwm",
"reserved", "reserved",
"reserved", "reserved";
rockchip,suspend-clkgating-setting=<0x0033 0x0033>;
#clock-cells = <1>;
};
clk_gates12: gate-clk@0190 {
compatible = "rockchip,rk3188-gate-clk";
reg = <0x0190 0x4>;
clocks =
<&clk_core0>, <&clk_core1>,
<&clk_core2>, <&clk_core3>,
<&clk_l2ram>, <&aclk_core_m0>,
<&aclk_core_mp>, <&atclk_core>,
<&pclk_dbg_src>, <&pclk_dbg_src>,
<&pclk_dbg_src>, <&pclk_dbg_src>,
<&dummy>, <&dummy>,
<&dummy>, <&dummy>;
clock-output-names =
"clk_core0", "clk_core1",
"clk_core2", "clk_core3",
"clk_l2ram", "aclk_core_m0",
"aclk_core_mp", "atclk_core",
"pclk_dbg_src", "g_dbg_core_clk",
"g_cs_dbg_clk", "g_pclk_core_niu",
"reserved", "reserved",
"reserved", "reserved";
rockchip,suspend-clkgating-setting=<0x0ff1 0x0ff1>;
#clock-cells = <1>;
};
clk_gates13: gate-clk@0194 {
compatible = "rockchip,rk3188-gate-clk";
reg = <0x0194 0x4>;
clocks =
<&clk_sdmmc>, <&clk_sdio0>,
<&clk_sdio1>, <&clk_emmc>,
<&xin24m>, <&xin24m>,
<&xin24m>, <&xin32k>,
<&aclk_bus_src>, <&xin12m>,
<&xin24m>, <&xin24m>,
<&dummy>, <&aclk_hevc>,
<&clk_hevc_cabac>, <&clk_hevc_core>;
clock-output-names =
"clk_sdmmc", "clk_sdio0",
"clk_sdio1", "clk_emmc",
"clk_otgphy0", "clk_otgphy1",
"clk_otgphy2", "clk_otg_adp",
"g_clk_c2c_host", "g_clk_ehci1_12m",
"g_clk_lcdc_pwm0", "g_clk_lcdc_pwm1",
"g_clk_wifi", "aclk_hevc",
"clk_hevc_cabac", "clk_hevc_core";
rockchip,suspend-clkgating-setting=<0x0 0x0>;
#clock-cells = <1>;
};
clk_gates14: gate-clk@0198 {
compatible = "rockchip,rk3188-gate-clk";
reg = <0x0198 0x4>;
clocks =
<&dummy>, <&pclk_pd_alive>,
<&pclk_pd_alive>, <&pclk_pd_alive>,
<&pclk_pd_alive>, <&pclk_pd_alive>,
<&pclk_pd_alive>, <&pclk_pd_alive>,
<&pclk_pd_alive>, <&dummy>,
<&dummy>, <&pclk_pd_alive>,
<&pclk_pd_alive>, <&dummy>,
<&dummy>, <&dummy>;
clock-output-names =
"reserved", "g_pclk_gpio1",
"g_pclk_gpio2", "g_pclk_gpio3",
"g_pclk_gpio4", "g_pclk_gpio5",
"g_pclk_gpio6", "g_pclk_gpio7",
"g_pclk_gpio8", "reserved",
"reserved", "g_pclk_grf",
"g_p_alive_niu", "reserved",
"reserved", "reserved";
//rockchip,suspend-clkgating-setting=<0xffff 0xffff>;
rockchip,suspend-clkgating-setting=<0x19fe 0x19fe>;
#clock-cells = <1>;
};
clk_gates15: gate-clk@019c {
compatible = "rockchip,rk3188-gate-clk";
reg = <0x019c 0x4>;
clocks =
<&aclk_rga>, <&hclk_vio>,
<&clk_gates15 11>, <&hclk_vio>,
<&dummy>, <&clk_gates15 11>,
<&hclk_vio>, <&clk_gates15 12>,
<&hclk_vio>, <&dummy>,
<&dummy>, <&aclk_vio0>,
<&aclk_vio1>, <&aclk_rga>,
<&clk_gates15 11>, <&hclk_vio>;
clock-output-names =
"reserved", /*"g_aclk_rga"*/ "g_hclk_rga",
"g_aclk_iep", "g_hclk_iep",
"g_aclk_lcdc_iep", "g_aclk_lcdc0",
"g_hclk_lcdc0", "g_aclk_lcdc1",
"g_hclk_lcdc1", "reserved", /* "g_h_vio_ahb" */
"reserved",/*"g_hclk_vio_niu"*/ "g_aclk_vio0_niu",
"g_aclk_vio1_niu", "reserved",/*"g_aclk_rga_niu"*/
"g_aclk_vip", "g_hclk_vip";
rockchip,suspend-clkgating-setting=<0x0 0x0>;
#clock-cells = <1>;
};
clk_gates16: gate-clk@01a0 {
compatible = "rockchip,rk3188-gate-clk";
reg = <0x01a0 0x4>;
clocks =
<&pclkin_cif>, <&hclk_vio>,
<&clk_gates15 12>, <&pclkin_isp>,
<&hclk_vio>, <&hclk_vio>,
<&hclk_vio>, <&hclk_vio>,
<&hclk_vio>, <&hclk_vio>,
<&dummy>, <&dummy>,
<&dummy>, <&dummy>,
<&dummy>, <&dummy>;
clock-output-names =
"g_pclkin_cif", "g_hclk_isp",
"g_aclk_isp", "g_pclkin_isp",
"g_p_mipi_dsi0", "g_p_mipi_dsi1",
"g_p_mipi_csi", "g_pclk_lvds_phy",
"g_pclk_edp_ctrl", "g_p_hdmi_ctrl",
"reserved", "reserved", /* bit10:"g_hclk_vio2_h2p" bit11: "g_pclk_vio2_h2p" */
"reserved", "reserved",
"reserved", "reserved";
rockchip,suspend-clkgating-setting=<0x0 0x0>;
#clock-cells = <1>;
};
clk_gates17: gate-clk@01a4 {
compatible = "rockchip,rk3188-gate-clk";
reg = <0x01a4 0x4>;
clocks =
<&pclk_pd_pmu>, <&pclk_pd_pmu>,
<&pclk_pd_pmu>, <&pclk_pd_pmu>,
<&pclk_pd_pmu>, <&dummy>,
<&dummy>, <&dummy>,
<&dummy>, <&dummy>,
<&dummy>, <&dummy>,
<&dummy>, <&dummy>,
<&dummy>, <&dummy>;
clock-output-names =
"g_pclk_pmu", "g_pclk_intmem1",
"g_pclk_pmu_niu", "g_pclk_sgrf",
"g_pclk_gpio0", "reserved",
"reserved", "reserved",
"reserved", "reserved",
"reserved", "reserved",
"reserved", "reserved",
"reserved", "reserved";
rockchip,suspend-clkgating-setting=<0x01f 0x01f>;
#clock-cells = <1>;
};
clk_gates18: gate-clk@01a8 {
compatible = "rockchip,rk3188-gate-clk";
reg = <0x01a8 0x4>;
clocks =
<&clk_gpu>, <&dummy>,
<&dummy>, <&dummy>,
<&dummy>, <&dummy>,
<&dummy>, <&dummy>,
<&dummy>, <&dummy>,
<&dummy>, <&dummy>,
<&dummy>, <&dummy>,
<&dummy>, <&dummy>;
clock-output-names =
"reserved", /*"g_aclk_gpu",*/ "reserved",
"reserved", "reserved",
"reserved", "reserved",
"reserved", "reserved",
"reserved", "reserved",
"reserved", "reserved",
"reserved", "reserved",
"reserved", "reserved";
rockchip,suspend-clkgating-setting=<0x0 0x0>;
#clock-cells = <1>;
};
};
};
};
};