关键词：rk3128-dram-default-timing.dtsi ,linux_3.10,rockchip,dts
dts — rk3128-dram-default-timing.dtsi
/*
* Copyright (c) 2017 Fuzhou Rockchip Electronics Co., Ltd
*
* This file is dual-licensed: you can use it either under the terms
* of the GPL or the X11 license, at your option. Note that this dual
* licensing only applies to this file, and not this project as a
* whole.
*
* a) This library is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
* published by the Free Software Foundation; either version 2 of the
* License, or (at your option) any later version.
*
* This library is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* Or, alternatively,
*
* b) Permission is hereby granted, free of charge, to any person
* obtaining a copy of this software and associated documentation
* files (the "Software"), to deal in the Software without
* restriction, including without limitation the rights to use,
* copy, modify, merge, publish, distribute, sublicense, and/or
* sell copies of the Software, and to permit persons to whom the
* Software is furnished to do so, subject to the following
* conditions:
*
* The above copyright notice and this permission notice shall be
* included in all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
* EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
* OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
* NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
* HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
* OTHER DEALINGS IN THE SOFTWARE.
*/
#include <dt-bindings/clock/rockchip-ddr.h>
#include <dt-bindings/memory/rk3128-dram.h>
/ {
ddr_timing: ddr_timing {
compatible = "rockchip,ddr-timing";
ddr3_speed_bin = <DDR3_DEFAULT>;
pd_idle = <0x40>;
sr_idle = <0x1>;
auto_pd_dis_freq = <300>;
auto_sr_dis_freq = <300>;
ddr3_dll_dis_freq = <300>;
lpddr2_dll_dis_freq = <300>;
phy_dll_dis_freq = <266>;
ddr3_odt_dis_freq = <333>;
phy_ddr3_odt_disb_freq = <333>;
ddr3_drv = <DDR3_DS_40ohm>;
ddr3_odt = <DDR3_ODT_120ohm>;
phy_ddr3_clk_drv = <PHY_RON_44ohm>;
phy_ddr3_cmd_drv = <PHY_RON_44ohm>;
phy_ddr3_dqs_drv = <PHY_RON_44ohm>;
phy_ddr3_odt = <PHY_RTT_216ohm>;
lpddr2_drv = <LP2_DS_34ohm>;
phy_lpddr2_clk_drv = <PHY_RON_44ohm>;
phy_lpddr2_cmd_drv = <PHY_RON_44ohm>;
phy_lpddr2_dqs_drv = <PHY_RON_44ohm>;
};
};
ltage_map= <925000 950000 975000 1000000 1025000 1050000 1075000 1100000 1125000 1150000 1175000 1200000 1225000 1250000 1275000 1300000 1325000 1350000 1375000 1400000>;
rockchip,pwm_voltage= <1000000>;
rockchip,pwm_min_voltage= <925000>;
rockchip,pwm_max_voltage= <1400000>;
rockchip,pwm_suspend_voltage= <950000>;
rockchip,pwm_coefficient= <475>;
regulators {
#address-cells = <1>;
#size-cells = <0>;
pwm_reg0: regulator@0 {
regulator-compatible = "pwm_dcdc1";
regulator-name= "vdd_logic";
regulator-min-microvolt = <925000>;
regulator-max-microvolt = <1400000>;
regulator-always-on;
regulator-boot-on;
};
};
};
codec_hdmi_i2s: codec-hdmi-i2s {
compatible = "hdmi-i2s";
};
codec_hdmi_spdif: codec-hdmi-spdif {
compatible = "hdmi-spdif";
};
rockchip-hdmi-i2s {
compatible = "rockchip-hdmi-i2s";
dais {
dai0 {
audio-codec = <&codec_hdmi_i2s>;
audio-controller = <&i2s>;
format = "i2s";
//continuous-clock;
//bitclock-inversion;
//frame-inversion;
//bitclock-master;
//frame-master;
};
};
};
rockchip-hdmi-spdif {
compatible = "rockchip-hdmi-spdif";
dais {
dai0 {
audio-codec = <&codec_hdmi_spdif>;
audio-controller = <&spdif>;
};
};
};
rockchip-rt5631 {
compatible = "rockchip-rt5631";
dais {
dai0 {
audio-codec = <&rt5631>;
audio-controller = <&i2s>;
format = "i2s";
//continuous-clock;
//bitclock-inversion;
//frame-inversion;
//bitclock-master;
//frame-master;
};
};
};
usb_control {
compatible = "rockchip,rk3288-usb-control";
otg_drv_gpio = <&gpio0 GPIO_B4 GPIO_ACTIVE_LOW>;
rockchip,remote_wakeup;
rockchip,usb_irq_wakeup;
};
};
&pinctrl {
gpio0_gpio {
gpio0_c2: gpio0-c2 {
rockchip,pins = <GPIO0_C2>;
rockchip,pull = <VALUE_PULL_DOWN>;
};
//to add
};
gpio7_gpio {
gpio7_b7: gpio7-b7 {
rockchip,pins = <GPIO7_B7>;
rockchip,pull = <VALUE_PULL_UP>;
};
//to add
};
//could add other pinctrl definition such as gpio
};
&emmc {
clock-frequency = <100000000>;
clock-freq-min-max = <400000 100000000>;
supports-highspeed;
supports-emmc;
bootpart-no-access;
supports-DDR_MODE;
caps2-mmc-hs200;
ignore-pm-notify;
keep-power-in-suspend;
status = "okay";
};
&sdmmc {
clock-frequency = <50000000>;
clock-freq-min-max = <400000 50000000>;
supports-highspeed;
supports-sd;
broken-cd;
card-detect-delay = <200>;
ignore-pm-notify;
keep-power-in-suspend;
vmmc-supply = <&ldo1_reg>;
status = "okay";
};
&sdio {
clock-frequency = <50000000>;
clock-freq-min-max = <200000 50000000>;
supports-highspeed;
supports-sdio;
ignore-pm-notify;
keep-power-in-suspend;
//cap-sdio-irq;
status = "okay";
};
&spi0 {
status = "disabled";
max-freq = <48000000>;
/*
spi_test@00 {
compatible = "rockchip,spi_test_bus0_cs0";
reg = <0>;
spi-max-frequency = <24000000>;
//spi-cpha;
//spi-cpol;
poll_mode = <0>;
type = <0>;
enable_dma = <0>;
};
spi_test@01 {
compatible = "rockchip,spi_test_bus0_cs1";
reg = <1>;
spi-max-frequency = <24000000>;
spi-cpha;
spi-cpol;
poll_mode = <0>;
type = <0>;
enable_dma = <0>;
};
*/
};
&spi1 {
status = "disabled";
max-freq = <48000000>;
/*
spi_test@10 {
compatible = "rockchip,spi_test_bus1_cs0";
reg = <0>;
spi-max-frequency = <24000000>;
//spi-cpha;
//spi-cpol;
poll_mode = <0>;
type = <0>;
enable_dma = <0>;
};
*/
};
&spi2 {
status = "disabled";
max-freq = <48000000>;
/*
spi_test@20 {
compatible = "rockchip,spi_test_bus2_cs0";
reg = <0>;
spi-max-frequency = <24000000>;
//spi-cpha;
//spi-cpol;
poll_mode = <0>;
type = <0>;
enable_dma = <0>;
};
spi_test@21 {
compatible = "rockchip,spi_test_bus2_cs1";
reg = <1>;
spi-max-frequency = <24000000>;
//spi-cpha;
//spi-cpol;
poll_mode = <0>;
type = <0>;
enable_dma = <0>;
};
*/
};
&uart_bt {
status = "okay";
dma-names = "!tx", "!rx";
pinctrl-0 = <&uart0_xfer &uart0_cts>;
};
&i2c0 {
status = "okay";
rk808: rk808@1b {
reg = <0x1b>;
status = "okay";
};
syr827: syr827@40 {
compatible = "silergy,syr82x";
reg = <0x40>;
status = "okay";
regulators {
#address-cells = <1>;
#size-cells = <0>;
syr827_dc1: regulator@0 {
reg = <0>;
regulator-compatible = "syr82x_dcdc1";
regulator-name = "vdd_arm";
regulator-min-microvolt = <712500>;
regulator-max-microvolt = <1500000>;
regulator-always-on;
regulator-boot-on;
regulator-initial-mode = <0x2>;
regulator-initial-state = <3>;
regulator-state-mem {
regulator-state-mode = <0x2>;
regulator-state-disabled;
regulator-state-uv = <900000>;
};
};
};
};
syr828: syr828@41 {
compatible = "silergy,syr82x";
reg = <0x41>;
status = "okay";
regulators {
#address-cells = <1>;
#size-cells = <0>;
syr828_dc1: regulator@0 {
reg = <0>;
regulator-compatible = "syr82x_dcdc1";
regulator-name = "vdd_gpu";
regulator-min-microvolt = <712500>;
regulator-max-microvolt = <1500000>;
//regulator-always-on;
//regulator-boot-on;
regulator-initial-mode = <0x2>;
regulator-initial-state = <3>;
regulator-state-mem {
regulator-state-mode = <0x2>;
regulator-state-disabled;
regulator-state-uv = <900000>;
};
};
};
};
act8846: act8846@5a {
reg = <0x5a>;
status = "okay";
};
CW2015@62 {
compatible = "cw201x";
reg = <0x62>;
dc_det_gpio = <&gpio0 GPIO_B0 GPIO_ACTIVE_LOW>;
bat_low_gpio = <&gpio0 GPIO_A7 GPIO_ACTIVE_LOW>;
chg_ok_gpio = <&gpio0 GPIO_B1 GPIO_ACTIVE_HIGH>;
bat_config_info = <0x15 0x81 0x5D 0x5C 0x58 0x5B 0x57 0x4B 0x49 0x4A 0x46 0x43 0x41
0x3A 0x38 0x30 0x26 0x1E 0x16 0x18 0x1C 0x2C 0x43 0x46 0x3C 0x93
0x09 0x9A 0x1A 0x33 0x6C 0x6E 0x6F 0x6D 0x6B 0x6C 0x3D 0x1C 0x61
0xB4 0x13 0x3F 0x52 0x87 0x8F 0x91 0x94 0x52 0x82 0x8C 0x92 0x96
0x87 0x95 0xC2 0xCB 0x2F 0x7D 0x72 0xA5 0xB5 0xC1 0x27 0x69>;
is_dc_charge = <1>;
is_usb_charge = <0>;
};
rtc@51 {
compatible = "rtc,hym8563";
reg = <0x51>;
irq_gpio = <&gpio0 GPIO_A4 IRQ_TYPE_EDGE_FALLING>;
};
};
&i2c1 {
status = "okay";
rtc@51 {
compatible = "nxp,pcf8563";
reg = <0x51>;
};
sensor@1d {
compatible = "gs_mma8452";
reg = <0x1d>;
type = <SENSOR_TYPE_ACCEL>;
irq-gpio = <&gpio8 GPIO_A0 IRQ_TYPE_LEVEL_LOW>;
irq_enable = <1>;
poll_delay_ms = <30>;
layout = <8>;
};
sensor@0d {
compatible = "ak8975";
reg = <0x0d>;
type = <SENSOR_TYPE_COMPASS>;
irq-gpio = <&gpio8 GPIO_A1 IRQ_TYPE_EDGE_RISING>;
irq_enable = <1>;
poll_delay_ms = <30>;
layout = <1>;
};
sensor@10 {
compatible = "ls_cm3218";
reg = <0x10>;
type = <SENSOR_TYPE_LIGHT>;
irq-gpio = <&gpio8 GPIO_A3 IRQ_TYPE_EDGE_FALLING>;
irq_enable = <1>;
poll_delay_ms = <30>;
layout = <1>;
};
/*
mpu6050:mpu@68{
compatible = "mpu6050";
reg = <0x68>;
mpu-int_config = <0x10>;
mpu-level_shifter = <0>;
mpu-orientation = <1 0 0 0 1 0 0 0 1>;
orientation-x= <1>;
orientation-y= <0>;
orientation-z= <1>;
irq-gpio = <&gpio8 GPIO_A0 IRQ_TYPE_LEVEL_LOW>;
mpu-debug = <0>;
};
ak8963:compass@0d{
compatible = "ak8963";
reg = <0x0d>;
compass-bus = <0>;
compass-adapt_num = <0>;
compass-orientation = <1 0 0 0 1 0 0 0 1>;
orientation-x= <0>;
orientation-y= <0>;
orientation-z= <1>;
compass-debug = <1>;
status = "disabled";
};
ak8975:compass@0d{
compatible = "ak8975";
reg = <0x0d>;
compass-bus = <0>;
compass-adapt_num = <0>;
compass-orientation = <0 1 0 1 0 0 0 0 1>;
orientation-x= <0>;
orientation-y= <0>;
orientation-z= <0>;
compass-debug = <0>;
};
*/
};
&i2c2 {
status = "okay";
rt5631: rt5631@1a {
compatible = "rt5631";
reg = <0x1a>;
phone_det_level = <1>;
};
};
&i2c3 {
status = "okay";
};
&i2c4 {
status = "okay";
ts@01 {
compatible = "ct,vtl_ts";
reg = <0x01>;
screen_max_x = <2048>;
screen_max_y = <1536>;
xy_swap = <0>;
x_reverse = <0>;
y_reverse = <1>;
x_mul = <1>;
y_mul = <1>;
bin_ver = <1>;
irq_gpio_number = <&gpio7 GPIO_A6 IRQ_TYPE_LEVEL_LOW>;
rst_gpio_number = <&gpio7 GPIO_A5 GPIO_ACTIVE_HIGH>;
};
};
&i2c5 {
status = "disable";
};
&fb {
rockchip,disp-mode = <DUAL>;
rockchip,uboot-logo-on = <1>;
};
&rk_screen {
display-timings = <&disp_timings>;
};
/*lcdc0 as PRMRY(LCD),lcdc1 as EXTEND(HDMI)*/
&lcdc0 {
status = "okay";
rockchip,mirror = <NO_MIRROR>;
rockchip,cabc_mode = <0>;
rockchip,iommu-enabled = <0>;
power_ctr: power_ctr {
rockchip,debug = <0>;
lcd_en:lcd_en {
rockchip,power_type = <GPIO>;
gpios = <&gpio7 GPIO_A3 GPIO_ACTIVE_HIGH>;
rockchip,delay = <10>;
};
/*lcd_cs:lcd_cs {
rockchip,power_type = <REGULATOR>;
rockchip,delay = <10>;
};
lcd_rst:lcd_rst {
rockchip,power_type = <GPIO>;
gpios = <&gpio3 GPIO_D6 GPIO_ACTIVE_HIGH>;
rockchip,delay = <5>;
};*/
};
};
&lcdc1 {
status = "okay";
rockchip,mirror = <NO_MIRROR>;
rockchip,iommu-enabled = <0>;
};
&hdmi {
status = "okay";
rockchip,hdmi_video_source = <DISPLAY_SOURCE_LCDC1>;
};
&adc {
status = "okay";
key {
compatible = "rockchip,key";
io-channels = <&adc 1>;
vol-up-key {
linux,code = <115>;
label = "volume up";
rockchip,adc_value = <1>;
};
vol-down-key {
linux,code = <114>;
label = "volume down";
rockchip,adc_value = <170>;
};
power-key {
gpios = <&gpio0 GPIO_A5 GPIO_ACTIVE_LOW>;
linux,code = <116>;
label = "power";
gpio-key,wakeup;
};
back-key {
linux,code = <158>;
label = "back";
rockchip,adc_value = <355>;
};
/*
home-key {
linux,code = <102>;
label = "home";
rockchip,adc_value = <746>;
};
back-key {
linux,code = <158>;
label = "back";
rockchip,adc_value = <560>;
};
*/
camera-key {
linux,code = <212>;
label = "camera";
rockchip,adc_value = <450>;
};
};
};
&pwm0 {
status = "okay";
};
&pwm1 {
status = "okay";
};
&clk_core_dvfs_table {
operating-points = <
/* KHz uV */
126000 900000
216000 900000
312000 900000
408000 900000
600000 900000
696000 950000
816000 1000000
1008000 1050000
1200000 1100000
1416000 1200000
1512000 1300000
1608000 1350000
// 1704000 1350000
// 1800000 1400000
>;
status="okay";
};
&clk_gpu_dvfs_table {
operating-points = <
/* KHz uV */
100000 900000
200000 900000
300000 950000
400000 1150000
500000 1200000
// 600000 1250000
>;
status="okay";
};
&clk_ddr_dvfs_table {
operating-points = <
/* KHz uV */
200000 1000000
300000 1000000
420000 1050000
533000 1100000
>;
freq-table = <
/*status freq(KHz)*/
SYS_STATUS_NORMAL 400000
SYS_STATUS_SUSPEND 200000
SYS_STATUS_VIDEO_1080P 240000
SYS_STATUS_VIDEO_4K 400000
SYS_STATUS_PERFORMANCE 528000
SYS_STATUS_DUALVIEW 400000
SYS_STATUS_BOOST 324000
SYS_STATUS_ISP 533000
>;
bd-freq-table = <
/* bandwidth freq */
5000 800000
3500 456000
2600 396000
2000 324000
>;
auto-freq-table = <
240000
324000
396000
528000
>;
auto-freq=<1>;
status="okay";
};
/include/ "act8846.dtsi"
&act8846 {
gpios =<&gpio7 GPIO_A1 GPIO_ACTIVE_LOW>,<&gpio0 GPIO_B2 GPIO_ACTIVE_HIGH>;
act8846,system-power-controller;
regulators {
dcdc1_reg: regulator@0{
regulator-name= "act_dcdc1";
regulator-min-microvolt = <1200000>;
regulator-max-microvolt = <1200000>;
regulator-always-on;
regulator-boot-on;
};
dcdc2_reg: regulator@1 {
regulator-name= "vccio";
regulator-min-microvolt = <3300000>;
regulator-max-microvolt = <3300000>;
regulator-initial-state = <3>;
regulator-state-mem {
regulator-state-enabled;
regulator-state-uv = <3300000>;
};
};
dcdc3_reg: regulator@2 {
regulator-name= "vdd_logic";
regulator-min-microvolt = <700000>;
regulator-max-microvolt = <1500000>;
regulator-initial-state = <3>;
regulator-state-mem {
regulator-state-enabled;
regulator-state-uv = <1000000>;
};
};
dcdc4_reg: regulator@3 {
regulator-name= "act_dcdc4";
regulator-min-microvolt = <2000000>;
regulator-max-microvolt = <2000000>;
regulator-initial-state = <3>;
regulator-state-mem {
regulator-state-enabled;
regulator-state-uv = <2000000>;
};
};
ldo1_reg: regulator@4 {
regulator-name= "vccio_sd";
regulator-min-microvolt = <1800000>;
regulator-max-microvolt = <3300000>;
};
ldo2_reg: regulator@5 {
regulator-name= "act_ldo2";
regulator-min-microvolt = <1000000>;
regulator-max-microvolt = <1000000>;
};
ldo3_reg: regulator@6 {
regulator-name= "act_ldo3";
regulator-min-microvolt = <3300000>;
regulator-max-microvolt = <3300000>;
};
ldo4_reg:regulator@7 {
regulator-name= "act_ldo4";
regulator-min-microvolt = <3300000>;
regulator-max-microvolt = <3300000>;
};
ldo5_reg: regulator@8 {
regulator-name= "act_ldo5";
regulator-min-microvolt = <3300000>;
regulator-max-microvolt = <3300000>;
};
ldo6_reg: regulator@9 {
regulator-name= "act_ldo6";
regulator-min-microvolt = <1000000>;
regulator-max-microvolt = <1000000>;
regulator-initial-state = <3>;
regulator-state-mem {
regulator-state-enabled;
};
};
ldo7_reg: regulator@10 {
regulator-name= "vcc_18";
regulator-min-microvolt = <1800000>;
regulator-max-microvolt = <1800000>;
regulator-initial-state = <3>;
regulator-state-mem {
regulator-state-enabled;
};
};
ldo8_reg: regulator@11 {
regulator-name= "act_ldo8";
regulator-min-microvolt = <1800000>;
regulator-max-microvolt = <1800000>;
};
};
};
/include/ "rk808.dtsi"
&rk808 {
gpios =<&gpio0 GPIO_A4 GPIO_ACTIVE_HIGH>,<&gpio0 GPIO_A0 GPIO_ACTIVE_LOW>;
rk808,system-power-controller;
regulators {
rk808_dcdc1_reg: regulator@0{
regulator-name= "vdd_arm";
regulator-always-on;
regulator-boot-on;
};
rk808_dcdc2_reg: regulator@1 {
regulator-name= "vdd_gpu";
regulator-always-on;
regulator-boot-on;
};
rk808_dcdc3_reg: regulator@2 {
regulator-name= "rk_dcdc3";
regulator-min-microvolt = <1200000>;
regulator-max-microvolt = <1200000>;
regulator-always-on;
regulator-boot-on;
};
rk808_dcdc4_reg: regulator@3 {
regulator-name= "vccio";
regulator-min-microvolt = <1800000>;
regulator-max-microvolt = <3300000>;
regulator-always-on;
regulator-boot-on;
};
rk808_ldo1_reg: regulator@4 {
regulator-name= "rk_ldo1";
regulator-min-microvolt = <3300000>;
regulator-max-microvolt = <3300000>;
regulator-always-on;
regulator-boot-on;
};
rk808_ldo2_reg: regulator@5 {
regulator-name= "rk_ldo2";
regulator-min-microvolt = <3300000>;
regulator-max-microvolt = <3300000>;
regulator-always-on;
regulator-boot-on;
};
rk808_ldo3_reg: regulator@6 {
regulator-name= "rk_ldo3";
regulator-min-microvolt = <1000000>;
regulator-max-microvolt = <1000000>;
regulator-always-on;
regulator-boot-on;
};
rk808_ldo4_reg:regulator@7 {
regulator-name= "rk_ldo4";
regulator-min-microvolt = <1800000>;
regulator-max-microvolt = <1800000>;
regulator-always-on;
regulator-boot-on;
};
rk808_ldo5_reg: regulator@8 {
regulator-name= "vcc_sd";
regulator-min-microvolt = <1800000>;
regulator-max-microvolt = <3300000>;
regulator-always-on;
regulator-boot-on;
};
rk808_ldo6_reg: regulator@9 {
regulator-name= "rk_ldo6";
regulator-min-microvolt = <1000000>;
regulator-max-microvolt = <1000000>;
regulator-always-on;
regulator-boot-on;
};
rk808_ldo7_reg: regulator@10 {
regulator-name= "rk_ldo7";
regulator-min-microvolt = <1800000>;
regulator-max-microvolt = <1800000>;
regulator-always-on;
regulator-boot-on;
};
rk808_ldo8_reg: regulator@11 {
regulator-name= "rk_ldo8";
regulator-min-microvolt = <3300000>;
regulator-max-microvolt = <3300000>;
regulator-always-on;
regulator-boot-on;
};
rk808_ldo9_reg: regulator@12 {
regulator-name= "rk_ldo9";
regulator-always-on;
regulator-boot-on;
};
rk808_ldo10_reg: regulator@13 {
regulator-name= "rk_ldo10";
regulator-always-on;
regulator-boot-on;
};
};
};
&lcdc_vdd_domain {
regulator-name = "vcc30_lcd";
};
&dpio_vdd_domain{
regulator-name = "vcc18_cif";
};
&flash0_vdd_domain{
regulator-name = "vcc_flash";
};
&flash1_vdd_domain{
regulator-name = "vcc_flash";
};
&apio3_vdd_domain{
regulator-name = "vccio_wl";
};
&apio5_vdd_domain{
regulator-name = "vccio";
};
&apio4_vdd_domain{
regulator-name = "vccio";
};
&apio1_vdd_domain{
regulator-name = "vccio";
};
&apio2_vdd_domain{
regulator-name = "vccio";
};
&sdmmc0_vdd_domain{
regulator-name = "vcc_sd";
};
;
};
&i2c0 {
pinctrl-names = "default";
pinctrl-0 = <&i2c0_xfer>;
};
&i2c1 {
pinctrl-names = "default";
pinctrl-0 = <&i2c1_xfer>;
};
&i2c2 {
pinctrl-names = "default";
pinctrl-0 = <&i2c2_xfer>;
};
&i2c3 {
pinctrl-names = "default";
pinctrl-0 = <&i2c3_xfer>;
};
&i2c4 {
pinctrl-names = "default";
pinctrl-0 = <&i2c4_xfer>;
};
&mmc0 {
pinctrl-names = "default";
pinctrl-0 = <&sd0_clk &sd0_cmd &sd0_cd &sd0_bus4>;
};
&mmc1 {
pinctrl-names = "default";
pinctrl-0 = <&sd1_clk &sd1_cmd &sd1_cd &sd1_bus4>;
};
&pwm0 {
pinctrl-names = "active";
pinctrl-0 = <&pwm0_out>;
};
&pwm1 {
pinctrl-names = "active";
pinctrl-0 = <&pwm1_out>;
};
&pwm2 {
pinctrl-names = "active";
pinctrl-0 = <&pwm2_out>;
};
&pwm3 {
pinctrl-names = "active";
pinctrl-0 = <&pwm3_out>;
};
&spi0 {
pinctrl-names = "default";
pinctrl-0 = <&spi0_clk &spi0_tx &spi0_rx &spi0_cs0>;
};
&spi1 {
pinctrl-names = "default";
pinctrl-0 = <&spi1_clk &spi1_tx &spi1_rx &spi1_cs0>;
};
&uart0 {
pinctrl-names = "default";
pinctrl-0 = <&uart0_xfer>;
};
&uart1 {
pinctrl-names = "default";
pinctrl-0 = <&uart1_xfer>;
};
&uart2 {
pinctrl-names = "default";
pinctrl-0 = <&uart2_xfer>;
};
&uart3 {
pinctrl-names = "default";
pinctrl-0 = <&uart3_xfer>;
};
&wdt {
compatible = "rockchip,rk3066-wdt", "snps,dw-wdt";
};
&emac {
compatible = "rockchip,rk3066-emac";
};
<3300000>;
regulator-max-microvolt = <3300000>;
regulator-always-on;
regulator-boot-on;
};
rk808_ldo3_reg: regulator@6 {
regulator-name= "rk_ldo3";
regulator-min-microvolt = <1000000>;
regulator-max-microvolt = <1000000>;
regulator-always-on;
regulator-boot-on;
};
rk808_ldo4_reg:regulator@7 {
regulator-name= "rk_ldo4";
regulator-min-microvolt = <1800000>;
regulator-max-microvolt = <1800000>;
regulator-always-on;
regulator-boot-on;
};
rk808_ldo5_reg: regulator@8 {
regulator-name= "vcc_sd";
regulator-min-microvolt = <1800000>;
regulator-max-microvolt = <3300000>;
regulator-always-on;
regulator-boot-on;
};
rk808_ldo6_reg: regulator@9 {
regulator-name= "rk_ldo6";
regulator-min-microvolt = <1000000>;
regulator-max-microvolt = <1000000>;
regulator-always-on;
regulator-boot-on;
};
rk808_ldo7_reg: regulator@10 {
regulator-name= "rk_ldo7";
regulator-min-microvolt = <1800000>;
regulator-max-microvolt = <1800000>;
regulator-always-on;
regulator-boot-on;
};
rk808_ldo8_reg: regulator@11 {
regulator-name= "rk_ldo8";
regulator-min-microvolt = <3300000>;
regulator-max-microvolt = <3300000>;
regulator-always-on;
regulator-boot-on;
};
rk808_ldo9_reg: regulator@12 {
regulator-name= "rk_ldo9";
regulator-always-on;
regulator-boot-on;
};
rk808_ldo10_reg: regulator@13 {
regulator-name= "rk_ldo10";
regulator-always-on;
regulator-boot-on;
};
};
};
&lcdc_vdd_domain {
regulator-name = "vcc30_lcd";
};
&dpio_vdd_domain{
regulator-name = "vcc18_cif";
};
&flash0_vdd_domain{
regulator-name = "vcc_flash";
};
&flash1_vdd_domain{
regulator-name = "vcc_flash";
};
&apio3_vdd_domain{
regulator-name = "vccio_wl";
};
&apio5_vdd_domain{
regulator-name = "vccio";
};
&apio4_vdd_domain{
regulator-name = "vccio";
};
&apio1_vdd_domain{
regulator-name = "vccio";
};
&apio2_vdd_domain{
regulator-name = "vccio";
};
&sdmmc0_vdd_domain{
regulator-name = "vcc_sd";
};
&dwc_control_usb {
usb_uart {
status = "disabled";
};
};
&rk3288_cif_sensor{
status = "okay";
};
-cells = <0>;
interrupts = <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 51 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 52 IRQ_TYPE_LEVEL_HIGH>;
interrupt-names = "otg-bvalid", "otg-id",
"linestate";
status = "disabled";
};
u2phy_host: host-port {
#phy-cells = <0>;
interrupts = <GIC_SPI 53 IRQ_TYPE_LEVEL_HIGH>;
interrupt-names = "linestate";
status = "disabled";
};
};
};
codec: codec@20030000 {
compatible = "rockchip,rk3128-codec";
reg = <0x20030000 0x4000>;
interrupts = <GIC_SPI 64 IRQ_TYPE_LEVEL_HIGH>;
boot_depop = <1>;
pa_enable_time = <1000>;
rockchip,grf = <&grf>;
clocks = <&cru PCLK_ACODEC>, <&cru SCLK_I2S1>;
clock-names = "g_pclk_acodec", "i2s_clk";
status = "disabled";
};
mipi_dphy: mipi-dphy@20038000 {
compatible = "rockchip,rk3128-mipi-dphy";
reg = <0x20038000 0x4000>;
clocks = <&cru SCLK_MIPI_24M>, <&cru PCLK_MIPIPHY>, <&cru HCLK_VIO_H2P>;
clock-names = "ref", "pclk", "h2p";
clock-output-names = "mipi_dphy_pll";
#clock-cells = <0>;
resets = <&cru SRST_MIPIPHY_P>;
reset-names = "apb";
power-domains = <&power RK3128_PD_VIO>;
rockchip,grf = <&grf>;
#phy-cells = <0>;
status = "disabled";
};
lvds: lvds@20038000 {
compatible = "rockchip,rk3126-lvds";
reg = <0x20038000 0x4000>, <0x10110000 0x100>;
reg-names = "mipi_lvds_phy", "mipi_lvds_ctl";
clocks = <&cru PCLK_MIPIPHY>, <&cru PCLK_MIPI>, <&cru HCLK_VIO_H2P>;
clock-names = "pclk_lvds", "pclk_lvds_ctl", "hclk_vio_h2p";
power-domains = <&power RK3128_PD_VIO>;
rockchip,grf = <&grf>;
status = "disabled";
ports {
#address-cells = <1>;
#size-cells = <0>;
lvds_in: port@0 {
reg = <0>;
lvds_in_vop: endpoint {
remote-endpoint = <&vop_out_lvds>;
};
};
};
};
timer@20044000 {
compatible = "rockchip,rk3128-timer", "rockchip,rk3288-timer";
reg = <0x20044000 0x20>;
interrupts = <GIC_SPI 28 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&xin24m>, <&cru PCLK_TIMER>;
clock-names = "timer", "pclk";
};
watchdog@2004c000 {
compatible = "snps,dw-wdt";
reg = <0x2004c000 0x100>;
clocks = <&cru PCLK_WDT>;
interrupts = <GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH>;
status = "disabled";
};
pwm0: pwm@20050000 {
compatible = "rockchip,rk3288-pwm";
reg = <0x20050000 0x10>;
#pwm-cells = <3>;
pinctrl-names = "active";
pinctrl-0 = <&pwm0_pin>;
clocks = <&cru PCLK_PWM>;
clock-names = "pwm";
status = "disabled";
};
pwm1: pwm@20050010 {
compatible = "rockchip,rk3288-pwm";
reg = <0x20050010 0x10>;
#pwm-cells = <3>;
pinctrl-names = "active";
pinctrl-0 = <&pwm1_pin>;
clocks = <&cru PCLK_PWM>;
clock-names = "pwm";
status = "disabled";
};
pwm2: pwm@20050020 {
compatible = "rockchip,rk3288-pwm";
reg = <0x20050020 0x10>;
#pwm-cells = <3>;
pinctrl-names = "active";
pinctrl-0 = <&pwm2_pin>;
clocks = <&cru PCLK_PWM>;
clock-names = "pwm";
status = "disabled";
};
pwm3: pwm@20050030 {
compatible = "rockchip,rk3288-pwm";
reg = <0x20050030 0x10>;
#pwm-cells = <3>;
pinctrl-names = "active";
pinctrl-0 = <&pwm3_pin>;
clocks = <&cru PCLK_PWM>;
clock-names = "pwm";
status = "disabled";
};
i2c1: i2c@20056000 {
compatible = "rockchip,rk3288-i2c";
reg = <0x20056000 0x1000>;
interrupts = <GIC_SPI 25 IRQ_TYPE_LEVEL_HIGH>;
#address-cells = <1>;
#size-cells = <0>;
clock-names = "i2c";
clocks = <&cru PCLK_I2C1>;
pinctrl-names = "default";
pinctrl-0 = <&i2c1_xfer>;
status = "disabled";
};
i2c2: i2c@2005a000 {
compatible = "rockchip,rk3288-i2c";
reg = <0x2005a000 0x1000>;
interrupts = <GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH>;
#address-cells = <1>;
#size-cells = <0>;
clock-names = "i2c";
clocks = <&cru PCLK_I2C2>;
pinctrl-names = "default";
pinctrl-0 = <&i2c2_xfer>;
status = "disabled";
};
i2c3: i2c@2005e000 {
compatible = "rockchip,rk3288-i2c";
reg = <0x2005e000 0x1000>;
interrupts = <GIC_SPI 27 IRQ_TYPE_LEVEL_HIGH>;
#address-cells = <1>;
#size-cells = <0>;
clock-names = "i2c";
clocks = <&cru PCLK_I2C3>;
pinctrl-names = "default";
pinctrl-0 = <&i2c3_xfer>;
status = "disabled";
};
uart0: serial@20060000 {
compatible = "rockchip,rk3128-uart", "snps,dw-apb-uart";
reg = <0x20060000 0x100>;
interrupts = <GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>;
clock-frequency = <24000000>;
clocks = <&cru SCLK_UART0>, <&cru PCLK_UART0>;
clock-names = "baudclk", "apb_pclk";
reg-shift = <2>;
reg-io-width = <4>;
pinctrl-names = "default";
pinctrl-0 = <&uart0_xfer &uart0_cts &uart0_rts>;
status = "disabled";
};
uart1: serial@20064000 {
compatible = "rockchip,rk3128-uart", "snps,dw-apb-uart";
reg = <0x20064000 0x100>;
interrupts = <GIC_SPI 21 IRQ_TYPE_LEVEL_HIGH>;
clock-frequency = <24000000>;
clocks = <&cru SCLK_UART1>, <&cru PCLK_UART1>;
clock-names = "baudclk", "apb_pclk";
reg-shift = <2>;
reg-io-width = <4>;
pinctrl-names = "default";
pinctrl-0 = <&uart1_xfer &uart1_cts &uart1_rts>;
status = "disabled";
};
uart2: serial@20068000 {
compatible = "rockchip,rk3128-uart", "snps,dw-apb-uart";
reg = <0x20068000 0x100>;
interrupts = <GIC_SPI 22 IRQ_TYPE_LEVEL_HIGH>;
clock-frequency = <24000000>;
clocks = <&cru SCLK_UART2>, <&cru PCLK_UART2>;
clock-names = "baudclk", "apb_pclk";
reg-shift = <2>;
reg-io-width = <4>;
pinctrl-names = "default";
pinctrl-0 = <&uart2_xfer>;
status = "disabled";
};
saradc: saradc@2006c000 {
compatible = "rockchip,saradc";
reg = <0x2006c000 0x100>;
interrupts = <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>;
#io-channel-cells = <1>;
clocks = <&cru SCLK_SARADC>, <&cru PCLK_SARADC>;
clock-names = "saradc", "apb_pclk";
resets = <&cru SRST_SARADC>;
reset-names = "saradc-apb";
status = "disabled";
};
i2c0: i2c@20072000 {
compatible = "rockchip,rk3288-i2c";
reg = <0x20072000 0x1000>;
interrupts = <GIC_SPI 24 IRQ_TYPE_LEVEL_HIGH>;
#address-cells = <1>;
#size-cells = <0>;
clock-names = "i2c";
clocks = <&cru PCLK_I2C0>;
pinctrl-names = "default";
pinctrl-0 = <&i2c0_xfer>;
status = "disabled";
};
spi0: spi@20074000 {
compatible = "rockchip,rk3288-spi";
reg = <0x20074000 0x1000>;
interrupts = <GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH>;
pinctrl-names = "default";
pinctrl-0 = <&spi0_tx &spi0_rx &spi0_clk &spi0_cs0 &spi0_cs1>;
clock-names = "spiclk", "apb_pclk";
dmas = <&pdma 8>, <&pdma 9>;
dma-names = "tx", "rx";
#address-cells = <1>;
#size-cells = <0>;
status = "disabled";
};
gmac: eth@2008c000 {
compatible = "rockchip,rk3128-gmac";
reg = <0x2008c000 0x4000>;
interrupts = <GIC_SPI 56 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 57 IRQ_TYPE_LEVEL_HIGH>;
interrupt-names = "macirq", "eth_wake_irq";
rockchip,grf = <&grf>;
clocks = <&cru SCLK_MAC>,
<&cru SCLK_MAC_RX>, <&cru SCLK_MAC_TX>,
<&cru SCLK_MAC_REF>, <&cru SCLK_MAC_REFOUT>,
<&cru ACLK_GMAC>, <&cru PCLK_GMAC>;
clock-names = "stmmaceth",
"mac_clk_rx", "mac_clk_tx",
"clk_mac_ref", "clk_mac_refout",
"aclk_mac", "pclk_mac";
resets = <&cru SRST_GMAC>;
reset-names = "stmmaceth";
status = "disabled";
};
efuse: efuse@20090000 {
compatible = "rockchip,rk3128-efuse";
reg = <0x20090000 0x20>;
#address-cells = <1>;
#size-cells = <1>;
clocks = <&cru PCLK_EFUSE>;
clock-names = "pclk_efuse";
efuse_id: id@7 {
reg = <0x7 0x10>;
};
cpu_leakage: cpu_leakage@17 {
reg = <0x17 0x1>;
};
};
pinctrl: pinctrl {
compatible = "rockchip,rk3128-pinctrl";
rockchip,grf = <&grf>;
#address-cells = <1>;
#size-cells = <1>;
ranges;
gpio0: gpio0@2007c000 {
compatible = "rockchip,gpio-bank";
reg = <0x2007c000 0x100>;
interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&cru PCLK_GPIO0>;
gpio-controller;
#gpio-cells = <2>;
interrupt-controller;
#interrupt-cells = <2>;
};
gpio1: gpio1@20080000 {
compatible = "rockchip,gpio-bank";
reg = <0x20080000 0x100>;
interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&cru PCLK_GPIO1>;
gpio-controller;
#gpio-cells = <2>;
interrupt-controller;
#interrupt-cells = <2>;
};
gpio2: gpio2@20084000 {
compatible = "rockchip,gpio-bank";
reg = <0x20084000 0x100>;
interrupts = <GIC_SPI 38 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&cru PCLK_GPIO2>;
gpio-controller;
#gpio-cells = <2>;
interrupt-controller;
#interrupt-cells = <2>;
};
gpio3: gpio3@20088000 {
compatible = "rockchip,gpio-bank";
reg = <0x20088000 0x100>;
interrupts = <GIC_SPI 39 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&cru PCLK_GPIO3>;
gpio-controller;
#gpio-cells = <2>;
interrupt-controller;
#interrupt-cells = <2>;
};
pcfg_pull_default: pcfg_pull_default {
bias-pull-pin-default;
};
pcfg_output_high: pcfg-output-high {
output-high;
};
pcfg_pull_none: pcfg-pull-none {
bias-disable;
};
emmc {
emmc_clk: emmc-clk {
rockchip,pins = <2 RK_PA7 2 &pcfg_pull_none>;
};
emmc_cmd: emmc-cmd {
rockchip,pins = <1 RK_PC6 2 &pcfg_pull_default>;
};
emmc_cmd1: emmc-cmd1 {
rockchip,pins = <2 RK_PA4 2 &pcfg_pull_default>;
};
emmc_pwr: emmc-pwr {
rockchip,pins = <2 RK_PA5 2 &pcfg_pull_default>;
};
emmc_bus1: emmc-bus1 {
rockchip,pins = <1 RK_PD0 2 &pcfg_pull_default>;
};
emmc_bus4: emmc-bus4 {
rockchip,pins = <1 RK_PD0 2 &pcfg_pull_default>,
<1 RK_PD1 2 &pcfg_pull_default>,
<1 RK_PD2 2 &pcfg_pull_default>,
<1 RK_PD3 2 &pcfg_pull_default>;
};
emmc_bus8: emmc-bus8 {
rockchip,pins = <1 RK_PD0 2 &pcfg_pull_default>,
<1 RK_PD1 2 &pcfg_pull_default>,
<1 RK_PD2 2 &pcfg_pull_default>,
<1 RK_PD3 2 &pcfg_pull_default>,
<1 RK_PD4 2 &pcfg_pull_default>,
<1 RK_PD5 2 &pcfg_pull_default>,
<1 RK_PD6 2 &pcfg_pull_default>,
<1 RK_PD7 2 &pcfg_pull_default>;
};
};
i2c0 {
i2c0_xfer: i2c0-xfer {
rockchip,pins = <0 RK_PA0 1 &pcfg_pull_none>,
<0 RK_PA1 1 &pcfg_pull_none>;
};
};
i2c1 {
i2c1_xfer: i2c1-xfer {
rockchip,pins = <0 RK_PA2 1 &pcfg_pull_none>,
<0 RK_PA3 1 &pcfg_pull_none>;
};
};
i2c2 {
i2c2_xfer: i2c2-xfer {
rockchip,pins = <2 RK_PC4 3 &pcfg_pull_none>,
<2 RK_PC5 3 &pcfg_pull_none>;
};
};
i2c3 {
i2c3_xfer: i2c3-xfer {
rockchip,pins = <0 RK_PA6 1 &pcfg_pull_none>,
<0 RK_PA7 1 &pcfg_pull_none>;
};
};
uart0 {
uart0_xfer: uart0-xfer {
rockchip,pins = <2 RK_PD2 2 &pcfg_pull_default>,
<2 RK_PD3 2 &pcfg_pull_none>;
};
uart0_cts: uart0-cts {
rockchip,pins = <2 RK_PD5 2 &pcfg_pull_none>;
};
uart0_rts: uart0-rts {
rockchip,pins = <0 RK_PC1 2 &pcfg_pull_none>;
};
};
uart1 {
uart1_xfer: uart1-xfer {
rockchip,pins = <1 RK_PB1 2 &pcfg_pull_default>,
<1 RK_PB2 2 &pcfg_pull_default>;
};
uart1_cts: uart1-cts {
rockchip,pins = <1 RK_PB0 2 &pcfg_pull_none>;
};
uart1_rts: uart1-rts {
rockchip,pins = <1 RK_PB3 2 &pcfg_pull_none>;
};
};
uart2 {
uart2_xfer: uart2-xfer {
rockchip,pins = <1 RK_PC2 2 &pcfg_pull_default>,
<1 RK_PC3 2 &pcfg_pull_none>;
};
uart2_cts: uart2-cts {
rockchip,pins = <0 RK_PD1 1 &pcfg_pull_none>;
};
uart2_rts: uart2-rts {
rockchip,pins = <0 RK_PD0 1 &pcfg_pull_none>;
};
};
sdmmc {
sdmmc_clk: sdmmc-clk {
rockchip,pins = <1 RK_PC0 1 &pcfg_pull_none>;
};
sdmmc_cmd: sdmmc-cmd {
rockchip,pins = <1 RK_PB7 1 &pcfg_pull_default>;
};
sdmmc_wp: sdmmc-wp {
rockchip,pins = <1 RK_PA7 1 &pcfg_pull_default>;
};
sdmmc_pwren: sdmmc-pwren {
rockchip,pins = <1 RK_PB6 1 &pcfg_pull_default>;
};
sdmmc_bus4: sdmmc-bus4 {
rockchip,pins = <1 RK_PC2 1 &pcfg_pull_default>,
<1 RK_PC3 1 &pcfg_pull_default>,
<1 RK_PC4 1 &pcfg_pull_default>,
<1 RK_PC5 1 &pcfg_pull_default>;
};
};
sdio {
sdio_clk: sdio-clk {
rockchip,pins = <1 RK_PA0 2 &pcfg_pull_none>;
};
sdio_cmd: sdio-cmd {
rockchip,pins = <0 RK_PA3 2 &pcfg_pull_default>;
};
sdio_pwren: sdio-pwren {
rockchip,pins = <0 RK_PD6 1 &pcfg_pull_default>;
};
sdio_bus4: sdio-bus4 {
rockchip,pins = <1 RK_PA1 2 &pcfg_pull_default>,
<1 RK_PA2 2 &pcfg_pull_default>,
<1 RK_PA4 2 &pcfg_pull_default>,
<1 RK_PA5 2 &pcfg_pull_default>;
};
};
hdmi {
hdmii2c_xfer: hdmii2c-xfer {
rockchip,pins = <0 RK_PA6 2 &pcfg_pull_none>,
<0 RK_PA7 2 &pcfg_pull_none>;
};
hdmi_hpd: hdmi-hpd {
rockchip,pins = <0 RK_PB7 1 &pcfg_pull_none>;
};
hdmi_cec: hdmi-cec {
rockchip,pins = <0 RK_PC4 1 &pcfg_pull_none>;
};
};
i2s {
i2s_bus: i2s-bus {
rockchip,pins = <0 RK_PB0 1 &pcfg_pull_none>,
<0 RK_PB1 1 &pcfg_pull_none>,
<0 RK_PB3 1 &pcfg_pull_none>,
<0 RK_PB4 1 &pcfg_pull_none>,
<0 RK_PB5 1 &pcfg_pull_none>,
<0 RK_PB6 1 &pcfg_pull_none>;
};
i2s1_bus: i2s1-bus {
rockchip,pins = <1 RK_PA0 1 &pcfg_pull_none>,
<1 RK_PA1 1 &pcfg_pull_none>,
<1 RK_PA2 1 &pcfg_pull_none>,
<1 RK_PA3 1 &pcfg_pull_none>,
<1 RK_PA4 1 &pcfg_pull_none>,
<1 RK_PA5 1 &pcfg_pull_none>;
};
};
pwm0 {
pwm0_pin: pwm0-pin {
rockchip,pins = <0 RK_PD2 1 &pcfg_pull_none>;
};
};
pwm1 {
pwm1_pin: pwm1-pin {
rockchip,pins = <0 RK_PD3 1 &pcfg_pull_none>;
};
};
pwm2 {
pwm2_pin: pwm2-pin {
rockchip,pins = <1 RK_PD4 1 &pcfg_pull_none>;
};
};
pwm3 {
pwm3_pin: pwm3-pin {
rockchip,pins = <3 RK_PD2 1 &pcfg_pull_none>;
};
};
gmac {
rgmii_pins: rgmii-pins {
rockchip,pins = <2 RK_PB0 3 &pcfg_pull_default>,
<2 RK_PB1 3 &pcfg_pull_default>,
<2 RK_PB3 3 &pcfg_pull_default>,
<2 RK_PB4 3 &pcfg_pull_default>,
<2 RK_PB5 3 &pcfg_pull_default>,
<2 RK_PB6 3 &pcfg_pull_default>,
<2 RK_PC0 3 &pcfg_pull_default>,
<2 RK_PC1 3 &pcfg_pull_default>,
<2 RK_PC2 3 &pcfg_pull_default>,
<2 RK_PC3 3 &pcfg_pull_default>,
<2 RK_PD1 3 &pcfg_pull_default>,
<2 RK_PC4 4 &pcfg_pull_default>,
<2 RK_PC5 4 &pcfg_pull_default>,
<2 RK_PC6 4 &pcfg_pull_default>,
<2 RK_PC7 4 &pcfg_pull_default>;
};
rmii_pins: rmii-pins {
rockchip,pins = <2 RK_PB0 3 &pcfg_pull_default>,
<2 RK_PB4 3 &pcfg_pull_default>,
<2 RK_PB5 3 &pcfg_pull_default>,
<2 RK_PB6 3 &pcfg_pull_default>,
<2 RK_PB7 3 &pcfg_pull_default>,
<2 RK_PC0 3 &pcfg_pull_default>,
<2 RK_PC1 3 &pcfg_pull_default>,
<2 RK_PC3 3 &pcfg_pull_default>,
<2 RK_PC4 3 &pcfg_pull_default>,
<2 RK_PD1 3 &pcfg_pull_default>;
};
};
spdif {
spdif_tx: spdif-tx {
rockchip,pins = <3 RK_PD3 1 &pcfg_pull_none>;
};
};
spi {
spi0_clk: spi0-clk {
rockchip,pins = <1 RK_PB0 1 &pcfg_pull_default>;
};
spi0_cs0: spi0-cs0 {
rockchip,pins = <1 RK_PB3 1 &pcfg_pull_default>;
};
spi0_tx: spi0-tx {
rockchip,pins = <1 RK_PB1 1 &pcfg_pull_default>;
};
spi0_rx: spi0-rx {
rockchip,pins = <1 RK_PB2 1 &pcfg_pull_default>;
};
spi0_cs1: spi0-cs1 {
rockchip,pins = <1 RK_PB4 1 &pcfg_pull_default>;
};
spi1_clk: spi1-clk {
rockchip,pins = <2 RK_PA0 2 &pcfg_pull_default>;
};
spi1_cs0: spi1-cs0 {
rockchip,pins = <1 RK_PD6 3 &pcfg_pull_default>;
};
spi1_tx: spi1-tx {
rockchip,pins = <1 RK_PD5 3 &pcfg_pull_default>;
};
spi1_rx: spi1-rx {
rockchip,pins = <1 RK_PD4 3 &pcfg_pull_default>;
};
spi1_cs1: spi1-cs1 {
rockchip,pins = <1 RK_PD7 3 &pcfg_pull_default>;
};
spi2_clk: spi2-clk {
rockchip,pins = <0 RK_PB1 2 &pcfg_pull_default>;
};
spi2_cs0: spi2-cs0 {
rockchip,pins = <0 RK_PB6 2 &pcfg_pull_default>;
};
spi2_tx: spi2-tx {
rockchip,pins = <0 RK_PB3 2 &pcfg_pull_default>;
};
spi2_rx: spi2-rx {
rockchip,pins = <0 RK_PB5 2 &pcfg_pull_default>;
};
};
};
};
-cells = <1>;
};
/* reg[14:13]: reserved */
clk_edp_24m: edp_24m_mux {
compatible = "rockchip,rk3188-mux-con";
rockchip,bits = <15 1>;
clocks = <&edp_24m_clkin>, <&xin24m>;
clock-output-names = "clk_edp_24m";
#clock-cells = <0>;
};
};
clk_sel_con29: sel-con@00d4 {
compatible = "rockchip,rk3188-selcon";
reg = <0x00d4 0x4>;
#address-cells = <1>;
#size-cells = <1>;
ehci1phy_480m: ehci1phy_480m_mux {
compatible = "rockchip,rk3188-mux-con";
rockchip,bits = <0 2>;
clocks = <&dummy_cpll>, <&clk_gpll>, <&usbphy_480m>;
clock-output-names = "ehci1phy_480m";
#clock-cells = <0>;
};
ehci1phy_12m: ehci1phy_12m_mux {
compatible = "rockchip,rk3188-mux-con";
rockchip,bits = <2 1>;
clocks = <&clk_gates13 9>, <&ehci1phy_12m_div>;
clock-output-names = "ehci1phy_12m";
#clock-cells = <0>;
};
clkin_isp: clkin_isp {
compatible = "rockchip,rk3188-mux-con";
rockchip,bits = <3 1>;
clocks = <&clk_gates16 3>, <&pclkin_isp_inv>;
clock-output-names = "clkin_isp";
#clock-cells = <0>;
};
clkin_cif: clkin_cif {
compatible = "rockchip,rk3188-mux-con";
rockchip,bits = <4 1>;
clocks = <&clk_gates16 0>, <&pclkin_cif_inv>;
clock-output-names = "clkin_cif";
#clock-cells = <0>;
};
/* reg[5]: reserved */
dclk_lcdc1: dclk_lcdc1_mux {
compatible = "rockchip,rk3188-mux-con";
rockchip,bits = <6 2>;
clocks = <&clk_cpll>, <&clk_gpll>, <&clk_npll>;
clock-output-names = "dclk_lcdc1";
#clock-cells = <0>;
};
dclk_lcdc1_div: dclk_lcdc1_div {
compatible = "rockchip,rk3188-div-con";
rockchip,bits = <8 8>;
clocks = <&dclk_lcdc1>;
clock-output-names = "dclk_lcdc1";
rockchip,div-type = <CLK_DIVIDER_PLUS_ONE>;
#clock-cells = <0>;
rockchip,clkops-idx =
<CLKOPS_RATE_RK3288_DCLK_LCDC1>;
rockchip,flags = <CLK_SET_RATE_PARENT>;
};
};
clk_sel_con30: sel-con@00d8 {
compatible = "rockchip,rk3188-selcon";
reg = <0x00d8 0x4>;
#address-cells = <1>;
#size-cells = <1>;
aclk_rga_div: aclk_rga_div {
compatible = "rockchip,rk3188-div-con";
rockchip,bits = <0 5>;
clocks = <&aclk_rga>;
clock-output-names = "aclk_rga";
rockchip,div-type = <CLK_DIVIDER_PLUS_ONE>;
#clock-cells = <0>;
rockchip,clkops-idx =
<CLKOPS_RATE_MUX_DIV>;
};
/* reg[5]: reserved */
aclk_rga: aclk_rga_mux {
compatible = "rockchip,rk3188-mux-con";
rockchip,bits = <6 2>;
clocks = <&dummy_cpll>, <&clk_gpll>, <&usbphy_480m>;
clock-output-names = "aclk_rga";
#clock-cells = <0>;
#clock-init-cells = <1>;
};
clk_rga_div: clk_rga_div {
compatible = "rockchip,rk3188-div-con";
rockchip,bits = <8 5>;
clocks = <&clk_rga>;
clock-output-names = "clk_rga";
rockchip,div-type = <CLK_DIVIDER_PLUS_ONE>;
#clock-cells = <0>;
rockchip,clkops-idx =
<CLKOPS_RATE_MUX_DIV>;
};
/* reg[13]: reserved */
clk_rga: clk_rga_mux {
compatible = "rockchip,rk3188-mux-con";
rockchip,bits = <14 2>;
clocks = <&dummy_cpll>, <&clk_gpll>, <&usbphy_480m>;
clock-output-names = "clk_rga";
#clock-cells = <0>;
#clock-init-cells = <1>;
};
};
clk_sel_con31: sel-con@00dc {
compatible = "rockchip,rk3188-selcon";
reg = <0x00dc 0x4>;
#address-cells = <1>;
#size-cells = <1>;
aclk_vio0_div: aclk_vio0_div {
compatible = "rockchip,rk3188-div-con";
rockchip,bits = <0 5>;
clocks = <&aclk_vio0>;
clock-output-names = "aclk_vio0";
rockchip,div-type = <CLK_DIVIDER_PLUS_ONE>;
#clock-cells = <0>;
rockchip,clkops-idx =
<CLKOPS_RATE_MUX_DIV>;
rockchip,flags = <CLK_SET_RATE_NO_REPARENT>;
};
/* reg[5]: reserved */
aclk_vio0: aclk_vio0_mux {
compatible = "rockchip,rk3188-mux-con";
rockchip,bits = <6 2>;
clocks = <&clk_cpll>, <&clk_gpll>, <&usbphy_480m>;
clock-output-names = "aclk_vio0";
#clock-cells = <0>;
#clock-init-cells = <1>;
};
aclk_vio1_div: aclk_vio1_div {
compatible = "rockchip,rk3188-div-con";
rockchip,bits = <8 5>;
clocks = <&aclk_vio1>;
clock-output-names = "aclk_vio1";
rockchip,div-type = <CLK_DIVIDER_PLUS_ONE>;
#clock-cells = <0>;
rockchip,clkops-idx =
<CLKOPS_RATE_MUX_DIV>;
rockchip,flags = <CLK_SET_RATE_NO_REPARENT>;
};
/* reg[13]: reserved */
aclk_vio1: aclk_vio1_mux {
compatible = "rockchip,rk3188-mux-con";
rockchip,bits = <14 2>;
clocks = <&clk_cpll>, <&clk_gpll>, <&usbphy_480m>;
clock-output-names = "aclk_vio1";
#clock-cells = <0>;
#clock-init-cells = <1>;
};
};
clk_sel_con32: sel-con@00e0 {
compatible = "rockchip,rk3188-selcon";
reg = <0x00e0 0x4>;
#address-cells = <1>;
#size-cells = <1>;
clk_vepu_div: clk_vepu_div {
compatible = "rockchip,rk3188-div-con";
rockchip,bits = <0 5>;
clocks = <&clk_vepu>;
clock-output-names = "clk_vepu";
rockchip,div-type = <CLK_DIVIDER_PLUS_ONE>;
#clock-cells = <0>;
rockchip,clkops-idx =
<CLKOPS_RATE_MUX_DIV>;
};
/* reg[5]: reserved */
clk_vepu: clk_vepu_mux {
compatible = "rockchip,rk3188-mux-con";
rockchip,bits = <6 2>;
clocks = <&dummy_cpll>, <&clk_gpll>, <&usbphy_480m>;
clock-output-names = "clk_vepu";
#clock-cells = <0>;
#clock-init-cells = <1>;
};
clk_vdpu_div: clk_vdpu_div {
compatible = "rockchip,rk3188-div-con";
rockchip,bits = <8 5>;
clocks = <&clk_vdpu>;
clock-output-names = "clk_vdpu";
rockchip,div-type = <CLK_DIVIDER_PLUS_ONE>;
#clock-cells = <0>;
rockchip,clkops-idx =
<CLKOPS_RATE_MUX_DIV>;
};
/* reg[13]: reserved */
clk_vdpu: clk_vdpu_mux {
compatible = "rockchip,rk3188-mux-con";
rockchip,bits = <14 2>;
clocks = <&dummy_cpll>, <&clk_gpll>, <&usbphy_480m>;
clock-output-names = "clk_vdpu";
#clock-cells = <0>;
#clock-init-cells = <1>;
};
};
clk_sel_con33: sel-con@00e4 {
compatible = "rockchip,rk3188-selcon";
reg = <0x00e4 0x4>;
#address-cells = <1>;
#size-cells = <1>;
pclk_pd_pmu: pclk_pd_pmu_div {
compatible = "rockchip,rk3188-div-con";
rockchip,bits = <0 5>;
clocks = <&clk_gpll>;
clock-output-names = "pclk_pd_pmu";
rockchip,div-type = <CLK_DIVIDER_PLUS_ONE>;
#clock-cells = <0>;
#clock-init-cells = <1>;
};
/* reg[7:5]: reserved */
pclk_pd_alive: pclk_pd_alive {
compatible = "rockchip,rk3188-div-con";
rockchip,bits = <8 5>;
clocks = <&clk_gpll>;
clock-output-names = "pclk_pd_alive";
rockchip,div-type = <CLK_DIVIDER_PLUS_ONE>;
#clock-cells = <0>;
#clock-init-cells = <1>;
};
/* reg[15:13]: reserved */
};
clk_sel_con34: sel-con@00e8 {
compatible = "rockchip,rk3188-selcon";
reg = <0x00e8 0x4>;
#address-cells = <1>;
#size-cells = <1>;
clk_gpu_div: clk_gpu_div {
compatible = "rockchip,rk3188-div-con";
rockchip,bits = <0 5>;
clocks = <&clk_gpu>;
clock-output-names = "clk_gpu";
rockchip,div-type = <CLK_DIVIDER_PLUS_ONE>;
#clock-cells = <0>;
rockchip,clkops-idx =
<CLKOPS_RATE_MUX_DIV>;
rockchip,flags = <CLK_SET_RATE_PARENT_IN_ORDER>;
};
/* reg[5]: reserved */
clk_gpu: clk_gpu_mux {
compatible = "rockchip,rk3188-mux-con";
rockchip,bits = <6 2>;
clocks = <&dummy_cpll>, <&clk_gpll>, <&usbphy_480m>, <&clk_npll>;
clock-output-names = "clk_gpu";
#clock-cells = <0>;
#clock-init-cells = <1>;
};
clk_sdio1_div: clk_sdio1_div {
compatible = "rockchip,rk3188-div-con";
rockchip,bits = <8 6>;
clocks = <&clk_sdio1>;
clock-output-names = "clk_sdio1";
rockchip,div-type = <CLK_DIVIDER_PLUS_ONE>;
#clock-cells = <0>;
rockchip,clkops-idx =
<CLKOPS_RATE_MUX_EVENDIV>;
};
clk_sdio1: clk_sdio1_mux {
compatible = "rockchip,rk3188-mux-con";
rockchip,bits = <14 2>;
clocks = <&dummy_cpll>, <&clk_gpll>, <&xin24m>;
clock-output-names = "clk_sdio1";
#clock-cells = <0>;
};
};
clk_sel_con35: sel-con@00ec {
compatible = "rockchip,rk3188-selcon";
reg = <0x00ec 0x4>;
#address-cells = <1>;
#size-cells = <1>;
clk_tsp_div: clk_tsp_div {
compatible = "rockchip,rk3188-div-con";
rockchip,bits = <0 5>;
clocks = <&clk_tsp>;
clock-output-names = "clk_tsp";
rockchip,div-type = <CLK_DIVIDER_PLUS_ONE>;
#clock-cells = <0>;
rockchip,clkops-idx =
<CLKOPS_RATE_MUX_DIV>;
};
/* reg[5]: reserved */
clk_tsp: clk_tsp_mux {
compatible = "rockchip,rk3188-mux-con";
rockchip,bits = <6 2>;
clocks = <&dummy_cpll>, <&clk_gpll>, <&clk_npll>;
clock-output-names = "clk_tsp";
#clock-cells = <0>;
#clock-init-cells = <1>;
};
clk_tspout_div: clk_tspout_div {
compatible = "rockchip,rk3188-div-con";
rockchip,bits = <8 5>;
clocks = <&clk_tspout>;
clock-output-names = "clk_tspout";
rockchip,div-type = <CLK_DIVIDER_PLUS_ONE>;
#clock-cells = <0>;
rockchip,clkops-idx =
<CLKOPS_RATE_MUX_DIV>;
};
/* reg[13]: reserved */
clk_tspout: clk_tspout_mux {
compatible = "rockchip,rk3188-mux-con";
rockchip,bits = <14 2>;
clocks = <&dummy_cpll>, <&clk_gpll>, <&clk_npll>, <&io_27m_in>;
clock-output-names = "clk_tspout";
#clock-cells = <0>;
#clock-init-cells = <1>;
};
};
clk_sel_con36: sel-con@00f0 {
compatible = "rockchip,rk3188-selcon";
reg = <0x00f0 0x4>;
#address-cells = <1>;
#size-cells = <1>;
clk_core0: clk_core0_div {
compatible = "rockchip,rk3188-div-con";
rockchip,bits = <0 3>;
clocks = <&clk_core>;
clock-output-names = "clk_core0";
rockchip,div-type = <CLK_DIVIDER_PLUS_ONE>;
#clock-cells = <0>;
rockchip,clkops-idx = <CLKOPS_RATE_CORE_CHILD>;
};
/* reg[3]: reserved */
clk_core1: clk_core1_div {
compatible = "rockchip,rk3188-div-con";
rockchip,bits = <4 3>;
clocks = <&clk_core>;
clock-output-names = "clk_core1";
rockchip,div-type = <CLK_DIVIDER_PLUS_ONE>;
#clock-cells = <0>;
rockchip,clkops-idx = <CLKOPS_RATE_CORE_CHILD>;
};
/* reg[7]: reserved */
clk_core2: clk_core2_div {
compatible = "rockchip,rk3188-div-con";
rockchip,bits = <8 3>;
clocks = <&clk_core>;
clock-output-names = "clk_core2";
rockchip,div-type = <CLK_DIVIDER_PLUS_ONE>;
#clock-cells = <0>;
rockchip,clkops-idx = <CLKOPS_RATE_CORE_CHILD>;
};
/* reg[11]: reserved */
clk_core3: clk_core3_div {
compatible = "rockchip,rk3188-div-con";
rockchip,bits = <12 3>;
clocks = <&clk_core>;
clock-output-names = "clk_core3";
rockchip,div-type = <CLK_DIVIDER_PLUS_ONE>;
#clock-cells = <0>;
rockchip,clkops-idx = <CLKOPS_RATE_CORE_CHILD>;
};
/* reg[15]: reserved */
};
clk_sel_con37: sel-con@00f4 {
compatible = "rockchip,rk3188-selcon";
reg = <0x00f4 0x4>;
#address-cells = <1>;
#size-cells = <1>;
clk_l2ram: clk_l2ram_div {
compatible = "rockchip,rk3188-div-con";
rockchip,bits = <0 3>;
clocks = <&clk_core>;
clock-output-names = "clk_l2ram";
rockchip,div-type = <CLK_DIVIDER_PLUS_ONE>;
#clock-cells = <0>;
rockchip,clkops-idx = <CLKOPS_RATE_CORE_CHILD>;
};
/* reg[3]: reserved */
atclk_core: atclk_core_div {
compatible = "rockchip,rk3188-div-con";
rockchip,bits = <4 5>;
clocks = <&clk_core>;
clock-output-names = "atclk_core";
rockchip,div-type = <CLK_DIVIDER_PLUS_ONE>;
#clock-cells = <0>;
rockchip,clkops-idx = <CLKOPS_RATE_CORE_CHILD>;
};
pclk_dbg_src: pclk_core_dbg_div {
compatible = "rockchip,rk3188-div-con";
rockchip,bits = <9 5>;
clocks = <&clk_core>;
clock-output-names = "pclk_dbg_src";
rockchip,div-type = <CLK_DIVIDER_PLUS_ONE>;
#clock-cells = <0>;
rockchip,clkops-idx = <CLKOPS_RATE_CORE_CHILD>;
};
/* reg[15:14]: reserved */
};
clk_sel_con38: sel-con@00f8 {
compatible = "rockchip,rk3188-selcon";
reg = <0x00f8 0x4>;
#address-cells = <1>;
#size-cells = <1>;
clk_nandc0_div: clk_nandc0_div {
compatible = "rockchip,rk3188-div-con";
rockchip,bits = <0 5>;
clocks = <&clk_nandc0>;
clock-output-names = "clk_nandc0";
rockchip,div-type = <CLK_DIVIDER_PLUS_ONE>;
#clock-cells = <0>;
rockchip,clkops-idx =
<CLKOPS_RATE_MUX_DIV>;
};
/* reg[6:5]: reserved */
clk_nandc0: clk_nandc0_mux {
compatible = "rockchip,rk3188-mux-con";
rockchip,bits = <7 1>;
clocks = <&dummy_cpll>, <&clk_gpll>;
clock-output-names = "clk_nandc0";
#clock-cells = <0>;
};
clk_nandc1_div: clk_nandc1_div {
compatible = "rockchip,rk3188-div-con";
rockchip,bits = <8 5>;
clocks = <&clk_nandc1>;
clock-output-names = "clk_nandc1";
rockchip,div-type = <CLK_DIVIDER_PLUS_ONE>;
#clock-cells = <0>;
rockchip,clkops-idx =
<CLKOPS_RATE_MUX_DIV>;
};
/* reg[14:13]: reserved */
clk_nandc1: clk_nandc1_mux {
compatible = "rockchip,rk3188-mux-con";
rockchip,bits = <15 1>;
clocks = <&dummy_cpll>, <&clk_gpll>;
clock-output-names = "clk_nandc1";
#clock-cells = <0>;
};
};
clk_sel_con39: sel-con@00fc {
compatible = "rockchip,rk3188-selcon";
reg = <0x00fc 0x4>;
#address-cells = <1>;
#size-cells = <1>;
clk_spi2_div: clk_spi2_div {
compatible = "rockchip,rk3188-div-con";
rockchip,bits = <0 7>;
clocks = <&clk_spi2>;
clock-output-names = "clk_spi2";
rockchip,div-type = <CLK_DIVIDER_PLUS_ONE>;
#clock-cells = <0>;
rockchip,clkops-idx =
<CLKOPS_RATE_MUX_DIV>;
};
clk_spi2: clk_spi2_mux {
compatible = "rockchip,rk3188-mux-con";
rockchip,bits = <7 1>;
clocks = <&dummy_cpll>, <&clk_gpll>;
clock-output-names = "clk_spi2";
#clock-cells = <0>;
};
aclk_hevc_div: aclk_hevc_div {
compatible = "rockchip,rk3188-div-con";
rockchip,bits = <8 5>;
clocks = <&aclk_hevc>;
clock-output-names = "aclk_hevc";
rockchip,div-type = <CLK_DIVIDER_PLUS_ONE>;
#clock-cells = <0>;
rockchip,clkops-idx =
<CLKOPS_RATE_MUX_DIV>;
rockchip,flags = <CLK_SET_RATE_PARENT_IN_ORDER>;
};
/* reg[13]: reserved */
aclk_hevc: aclk_hevc_mux {
compatible = "rockchip,rk3188-mux-con";
rockchip,bits = <14 2>;
clocks = <&dummy_cpll>, <&clk_gpll>, <&clk_npll>;
clock-output-names = "aclk_hevc";
#clock-cells = <0>;
#clock-init-cells = <1>;
};
};
clk_sel_con40: sel-con@0100 {
compatible = "rockchip,rk3188-selcon";
reg = <0x0100 0x4>;
#address-cells = <1>;
#size-cells = <1>;
spdif_8ch_div: spdif_8ch_div {
compatible = "rockchip,rk3188-div-con";
rockchip,bits = <0 7>;
clocks = <&clk_spdif_pll>;
clock-output-names = "spdif_8ch_div";
rockchip,div-type = <CLK_DIVIDER_PLUS_ONE>;
#clock-cells = <0>;
};
/* reg[7]: reserved */
clk_spdif_8ch: spdif_8ch_clk_mux {
compatible = "rockchip,rk3188-mux-con";
rockchip,bits = <8 2>;
clocks = <&spdif_8ch_div>, <&spdif_8ch_frac>, <&xin12m>;
clock-output-names = "clk_spdif_8ch";
#clock-cells = <0>;
rockchip,clkops-idx =
<CLKOPS_RATE_RK3288_I2S>;
rockchip,flags = <CLK_SET_RATE_PARENT>;
};
/* reg[11:10]: reserved */
hclk_hevc: hclk_hevc_div {
compatible = "rockchip,rk3188-div-con";
rockchip,bits = <12 2>;
clocks = <&aclk_hevc>;
clock-output-names = "hclk_hevc";
rockchip,div-type = <CLK_DIVIDER_PLUS_ONE>;
#clock-cells = <0>;
#clock-init-cells = <1>;
};
/* reg[15:14]: reserved */
};
clk_sel_con41: sel-con@0104 {
compatible = "rockchip,rk3188-selcon";
reg = <0x0104 0x4>;
#address-cells = <1>;
#size-cells = <1>;
spdif_8ch_frac: spdif_8ch_frac {
compatible = "rockchip,rk3188-frac-con";
clocks = <&spdif_8ch_div>;
clock-output-names = "spdif_8ch_frac";
/* numerator denominator */
rockchip,bits = <0 32>;
rockchip,clkops-idx =
<CLKOPS_RATE_FRAC>;
#clock-cells = <0>;
};
};
clk_sel_con42: sel-con@0108 {
compatible = "rockchip,rk3188-selcon";
reg = <0x0108 0x4>;
#address-cells = <1>;
#size-cells = <1>;
clk_hevc_cabac_div: clk_hevc_cabac_div {
compatible = "rockchip,rk3188-div-con";
rockchip,bits = <0 5>;
clocks = <&clk_hevc_cabac>;
clock-output-names = "clk_hevc_cabac";
rockchip,div-type = <CLK_DIVIDER_PLUS_ONE>;
#clock-cells = <0>;
rockchip,clkops-idx =
<CLKOPS_RATE_MUX_DIV>;
rockchip,flags = <CLK_SET_RATE_PARENT_IN_ORDER>;
};
/* reg[5]: reserved */
clk_hevc_cabac: clk_hevc_cabac_mux {
compatible = "rockchip,rk3188-mux-con";
rockchip,bits = <6 2>;
clocks = <&dummy_cpll>, <&clk_gpll>, <&clk_npll>;
clock-output-names = "clk_hevc_cabac";
#clock-cells = <0>;
#clock-init-cells = <1>;
};
clk_hevc_core_div: clk_hevc_core_div {
compatible = "rockchip,rk3188-div-con";
rockchip,bits = <8 5>;
clocks = <&clk_hevc_core>;
clock-output-names = "clk_hevc_core";
rockchip,div-type = <CLK_DIVIDER_PLUS_ONE>;
#clock-cells = <0>;
rockchip,clkops-idx =
<CLKOPS_RATE_MUX_DIV>;
rockchip,flags = <CLK_SET_RATE_PARENT_IN_ORDER>;
};
/* reg[13]: reserved */
clk_hevc_core: clk_hevc_core_mux {
compatible = "rockchip,rk3188-mux-con";
rockchip,bits = <14 2>;
clocks = <&dummy_cpll>, <&clk_gpll>, <&clk_npll>;
clock-output-names = "clk_hevc_core";
#clock-cells = <0>;
#clock-init-cells = <1>;
};
};
};
/* Gate control regs */
clk_gate_cons {
compatible = "rockchip,rk-gate-cons";
#address-cells = <1>;
#size-cells = <1>;
ranges ;
clk_gates0: gate-clk@0160 {
compatible = "rockchip,rk3188-gate-clk";
reg = <0x0160 0x4>;
clocks =
<&dummy>, <&clk_apll>,
<&clk_gpll>, <&aclk_bus>,
<&hclk_bus>, <&pclk_bus>,
<&dummy>, <&aclk_bus>,
<&clk_dpll>, <&clk_gpll>,
<&clk_gpll>, <&clk_cpll>,
<&xin24m>, <&dummy>,
<&dummy>, <&dummy>;
clock-output-names =
"reserved", "reserved", /* do not use bit1 = "core_apll" */
"clk_arm_gpll", "g_aclk_bus",
"hclk_bus", "pclk_bus",
"reserved", "aclk_bus_2pmu",
"reserved", "reserved", /*"clk_ddr_dpll", "clk_ddr_gpll",*/
"reserved", "reserved", /*"clk_bus_gpll", "clk_bus_cpll",*/
"clk_acc_efuse", "reserved",
"reserved", "reserved";
rockchip,suspend-clkgating-setting=<0x0fff 0x0fff>;
#clock-cells = <1>;
};
clk_gates1: gate-clk@0164 {
compatible = "rockchip,rk3188-gate-clk";
reg = <0x0164 0x4>;
clocks =
<&xin24m>, <&xin24m>,
<&xin24m>, <&xin24m>,
<&xin24m>, <&xin24m>,
<&dummy>, <&dummy>,
<&clk_uart0_pll>, <&uart0_frac>,
<&clk_uart1_div>, <&uart1_frac>,
<&clk_uart2_div>, <&uart2_frac>,
<&clk_uart3_div>, <&uart3_frac>;
clock-output-names =
"clk_timer0", "clk_timer1",
"clk_timer2", "clk_timer3",
"clk_timer4", "clk_timer5",
"reserved", "reserved",
"clk_uart0_pll", "uart0_frac",
"clk_uart1_div", "uart1_frac",
"clk_uart2_div", "uart2_frac",
"clk_uart3_div", "uart3_frac";
rockchip,suspend-clkgating-setting=<0x0 0x0>;
#clock-cells = <1>;
};
clk_gates2: gate-clk@0168 {
compatible = "rockchip,rk3188-gate-clk";
reg = <0x0168 0x4>;
clocks =
<&aclk_peri>, <&aclk_peri>,
<&hclk_peri>, <&pclk_peri>,
<&dummy>, <&clk_mac_pll>,
<&clk_hsadc_pll>, <&clk_tsadc>,
<&clk_saradc>, <&clk_spi0>,
<&clk_spi1>, <&clk_spi2>,
<&clk_uart4_div>, <&uart4_frac>,
<&dummy>, <&dummy>;
clock-output-names =
"aclk_peri", "reserved", /*"g_aclk_periph",*/
"hclk_peri", "pclk_peri",
"reserved", "clk_mac_pll",
"clk_hsadc_pll", "clk_tsadc",
"clk_saradc", "clk_spi0",
"clk_spi1", "clk_spi2",
"clk_uart4_div", "uart4_frac",
"reserved", "reserved";
rockchip,suspend-clkgating-setting=<0x000f 0x000f>;
#clock-cells = <1>;
};
clk_gates3: gate-clk@016c {
compatible = "rockchip,rk3188-gate-clk";
reg = <0x016c 0x4>;
clocks =
<&aclk_vio0>, <&dclk_lcdc0>,
<&aclk_vio1>, <&dclk_lcdc1>,
<&clk_rga>, <&aclk_rga>,
<&ehci1phy_480m>, <&clk_cif_pll>,
<&dummy>, <&clk_vepu>,
<&dummy>, <&clk_vdpu>,
<&clk_edp_24m>, <&clk_edp>,
<&clk_isp>, <&clk_isp_jpe>;
clock-output-names =
"aclk_vio0", "dclk_lcdc0",
"aclk_vio1", "dclk_lcdc1",
"clk_rga", "aclk_rga",
"ehci1phy_480m", "clk_cif_pll",
/*Not use hclk_vpu_gate tmp, fixme*/
"reserved", "clk_vepu",
"reserved", "clk_vdpu",
"clk_edp_24m", "clk_edp",
"clk_isp", "clk_isp_jpe";
rockchip,suspend-clkgating-setting=<0x0000 0x0000>;
#clock-cells = <1>;
};
clk_gates4: gate-clk@0170 {
compatible = "rockchip,rk3188-gate-clk";
reg = <0x0170 0x4>;
clocks =
<&clk_i2s_out>, <&clk_i2s_pll>,
<&i2s_frac>, <&clk_i2s>,
<&spdif_div>, <&spdif_frac>,
<&clk_spdif>, <&spdif_8ch_div>,
<&spdif_8ch_frac>, <&clk_spdif_8ch>,
<&clk_tsp>, <&clk_tspout>,
<&clk_ddr>, <&clk_ddr>,
<&jtag_clkin>, <&dummy>;
clock-output-names =
"clk_i2s_out", "clk_i2s_pll",
"i2s_frac", "clk_i2s",
"spdif_div", "spdif_frac",
"clk_spdif", "spdif_8ch_div",
"spdif_8ch_frac", "clk_spdif_8ch",
"clk_tsp", "clk_tspout",
/* Not use these ddr gates */
"reserved", "reserved", /*"g_clk_ddrphy0", "g_clk_ddrphy1",*/
"clk_jtag", "reserved"; /*"testclk_gate_en";*/
rockchip,suspend-clkgating-setting=<0xf000 0xf000>;
#clock-cells = <1>;
};
clk_gates5: gate-clk@0174 {
compatible = "rockchip,rk3188-gate-clk";
reg = <0x0174 0x4>;
clocks =
<&clk_mac>, <&clk_mac>,
<&clk_mac>, <&clk_mac>,
<&clk_crypto>, <&clk_nandc0>,
<&clk_nandc1>, <&clk_gpu>,
<&pclk_pd_pmu>, <&xin24m>,
<&xin24m>, <&xin32k>,
<&xin24m>, <&xin24m>,
<&usbphy_480m>, <&xin24m>;
clock-output-names =
"g_clk_mac_rx", "g_clk_mac_tx",
"g_clk_mac_ref", "g_mac_refout",
"clk_crypto", "clk_nandc0",
"clk_nandc1", "clk_gpu",
"pclk_pd_pmu", "g_clk_pvtm_core",
"g_clk_pvtm_gpu", "g_hdmi_cec_clk",
"g_hdmi_hdcp_clk", "g_ps2c_clk",
"usbphy_480m", "g_mipidsi_24m";
rockchip,suspend-clkgating-setting=<0x0100 0x0100>;
#clock-cells = <1>;
};
clk_gates6: gate-clk@0178 {
compatible = "rockchip,rk3188-gate-clk";
reg = <0x0178 0x4>;
clocks =
<&hclk_peri>, <&pclk_peri>,
<&aclk_peri>, <&aclk_peri>,
<&pclk_peri>, <&pclk_peri>,
<&pclk_peri>, <&pclk_peri>,
<&pclk_peri>, <&pclk_peri>,
<&dummy>, <&pclk_peri>,
<&pclk_peri>, <&pclk_peri>,
<&pclk_peri>, <&pclk_peri>;
clock-output-names =
"g_hp_matrix", "g_pp_axi_matrix",
"g_ap_axi_matrix", "g_aclk_dmac2",
"g_pclk_spi0", "g_pclk_spi1",
"g_pclk_spi2", "g_pclk_ps2c",
"g_pclk_uart0", "g_pclk_uart1",
"reserved", "g_pclk_uart3",
"g_pclk_uart4", "g_pclk_i2c1",
"g_pclk_i2c3", "g_pclk_i2c4";
rockchip,suspend-clkgating-setting=<0x0003 0x0003>;
#clock-cells = <1>;
};
clk_gates7: gate-clk@017c {
compatible = "rockchip,rk3188-gate-clk";
reg = <0x017c 0x4>;
clocks =
<&pclk_peri>, <&pclk_peri>,
<&pclk_peri>, <&pclk_peri>,
<&hclk_peri>, <&hclk_peri>,
<&hclk_peri>, <&hclk_peri>,
<&hclk_peri>, <&hclk_peri>,
<&hclk_peri>, <&aclk_peri>,
<&hclk_peri>, <&hclk_peri>,
<&hclk_peri>, <&hclk_peri>;
clock-output-names =
"g_pclk_i2c5", "g_pclk_saradc",
"g_pclk_tsadc", "g_pclk_sim",
"g_hclk_otg0", "g_pmu_hclk_otg0",
"g_hclk_host0", "g_hclk_host1",
"g_hclk_ehci1", "g_hclk_usb_peri",
"g_hp_ahb_arbi", "g_aclk_peri_niu",
"g_h_emem_peri", "g_hclk_mem_peri",
"g_hclk_nandc0", "g_hclk_nandc1";
rockchip,suspend-clkgating-setting=<0x0c00 0xc000>;
#clock-cells = <1>;
};
clk_gates8: gate-clk@0180 {
compatible = "rockchip,rk3188-gate-clk";
reg = <0x0180 0x4>;
clocks =
<&aclk_peri>, <&pclk_peri>,
<&aclk_peri>, <&hclk_peri>,
<&hclk_peri>, <&hclk_peri>,
<&hclk_peri>, <&hclk_peri>,
<&hclk_peri>, <&hsadc_0_tsp>,
<&hsadc_1_tsp>, <&io_27m_in>,
<&aclk_peri>, <&dummy>,
<&dummy>, <&dummy>;
clock-output-names =
"g_aclk_gmac", "g_pclk_gmac",
"g_hclk_gps", "g_hclk_sdmmc",
"g_hclk_sdio0", "g_hclk_sdio1",
"g_hclk_emmc", "g_hclk_hsadc",
"g_hclk_tsp", "g_hsadc_0_tsp",
"g_hsadc_1_tsp", "g_clk_27m_tsp",
"g_aclk_peri_mmu", "reserved",
"reserved", "reserved";
rockchip,suspend-clkgating-setting=<0x0000 0x0000>;
#clock-cells = <1>;
};
clk_gates9: gate-clk@0184 {
compatible = "rockchip,rk3188-gate-clk";
reg = <0x0184 0x4>;
clocks =
<&dummy>, <&dummy>,
<&dummy>, <&dummy>,
<&dummy>, <&dummy>,
<&dummy>, <&dummy>,
<&dummy>, <&dummy>,
<&dummy>, <&dummy>,
<&dummy>, <&dummy>,
<&dummy>, <&dummy>;
clock-output-names =
"reserved", "reserved", /*"aclk_video_gate_en", "hclk_video_clock_en",*/
"reserved", "reserved",
"reserved", "reserved",
"reserved", "reserved",
"reserved", "reserved",
"reserved", "reserved",
"reserved", "reserved",
"reserved", "reserved";
rockchip,suspend-clkgating-setting=<0x0 0x0>;
#clock-cells = <1>;
};
clk_gates10: gate-clk@0188 {
compatible = "rockchip,rk3188-gate-clk";
reg = <0x0188 0x4>;
clocks =
<&pclk_bus>, <&pclk_bus>,
<&pclk_bus>, <&pclk_bus>,
<&aclk_bus>, <&aclk_bus>,
<&aclk_bus>, <&aclk_bus>,
<&hclk_bus>, <&hclk_bus>,
<&hclk_bus>, <&hclk_bus>,
<&aclk_bus>, <&aclk_bus>,
<&pclk_bus>, <&pclk_bus>;
clock-output-names =
"g_pclk_pwm", "g_pclk_timer",
"g_pclk_i2c0", "g_pclk_i2c2",
"g_aclk_intmem", "g_clk_intmem0",
"g_clk_intmem1", "g_clk_intmem2",
"g_hclk_i2s", "g_hclk_rom",
"g_hclk_spdif", "g_h_spdif_8ch",
"g_aclk_dmac1", "g_aclk_strc_sys",
"reserved", "reserved"; /*"g_p_ddrupctl0", "g_pclk_publ0";*/
//rockchip,suspend-clkgating-setting=<0xe2f1 0xe2f1>; // use sram mem no gating
rockchip,suspend-clkgating-setting=<0xf2f1 0xf2f1>; // pwm logic vol
#clock-cells = <1>;
};
clk_gates11: gate-clk@018c {
compatible = "rockchip,rk3188-gate-clk";
reg = <0x018c 0x4>;
clocks =
<&pclk_bus>, <&pclk_bus>,
<&pclk_bus>, <&pclk_bus>,
<&dummy>, <&dummy>,
<&aclk_bus>, <&hclk_bus>,
<&aclk_bus>, <&pclk_bus>,
<&pclk_bus>, <&pclk_bus>,
<&dummy>, <&dummy>,
<&dummy>, <&dummy>;
clock-output-names =
"reserved", "reserved", /*"g_p_ddrupctl1", "g_pclk_publ1",*/
"g_p_efuse_1024", "g_pclk_tzpc",
"reserved", "reserved", /*"g_nclk_ddrupctl0", "g_nclk_ddrupctl1"*/
"g_aclk_crypto", "g_hclk_crypto",
"g_aclk_ccp", "g_pclk_uart2",
"g_p_efuse_256", "g_pclk_rkpwm",
"reserved", "reserved",
"reserved", "reserved";
rockchip,suspend-clkgating-setting=<0x0033 0x0033>;
#clock-cells = <1>;
};
clk_gates12: gate-clk@0190 {
compatible = "rockchip,rk3188-gate-clk";
reg = <0x0190 0x4>;
clocks =
<&clk_core0>, <&clk_core1>,
<&clk_core2>, <&clk_core3>,
<&clk_l2ram>, <&aclk_core_m0>,
<&aclk_core_mp>, <&atclk_core>,
<&pclk_dbg_src>, <&pclk_dbg_src>,
<&pclk_dbg_src>, <&pclk_dbg_src>,
<&dummy>, <&dummy>,
<&dummy>, <&dummy>;
clock-output-names =
"clk_core0", "clk_core1",
"clk_core2", "clk_core3",
"clk_l2ram", "aclk_core_m0",
"aclk_core_mp", "atclk_core",
"pclk_dbg_src", "g_dbg_core_clk",
"g_cs_dbg_clk", "g_pclk_core_niu",
"reserved", "reserved",
"reserved", "reserved";
rockchip,suspend-clkgating-setting=<0x0ff1 0x0ff1>;
#clock-cells = <1>;
};
clk_gates13: gate-clk@0194 {
compatible = "rockchip,rk3188-gate-clk";
reg = <0x0194 0x4>;
clocks =
<&clk_sdmmc>, <&clk_sdio0>,
<&clk_sdio1>, <&clk_emmc>,
<&xin24m>, <&xin24m>,
<&xin24m>, <&xin32k>,
<&aclk_bus_src>, <&xin12m>,
<&xin24m>, <&xin24m>,
<&dummy>, <&aclk_hevc>,
<&clk_hevc_cabac>, <&clk_hevc_core>;
clock-output-names =
"clk_sdmmc", "clk_sdio0",
"clk_sdio1", "clk_emmc",
"clk_otgphy0", "clk_otgphy1",
"clk_otgphy2", "clk_otg_adp",
"g_clk_c2c_host", "g_clk_ehci1_12m",
"g_clk_lcdc_pwm0", "g_clk_lcdc_pwm1",
"g_clk_wifi", "aclk_hevc",
"clk_hevc_cabac", "clk_hevc_core";
rockchip,suspend-clkgating-setting=<0x0 0x0>;
#clock-cells = <1>;
};
clk_gates14: gate-clk@0198 {
compatible = "rockchip,rk3188-gate-clk";
reg = <0x0198 0x4>;
clocks =
<&dummy>, <&pclk_pd_alive>,
<&pclk_pd_alive>, <&pclk_pd_alive>,
<&pclk_pd_alive>, <&pclk_pd_alive>,
<&pclk_pd_alive>, <&pclk_pd_alive>,
<&pclk_pd_alive>, <&dummy>,
<&dummy>, <&pclk_pd_alive>,
<&pclk_pd_alive>, <&dummy>,
<&dummy>, <&dummy>;
clock-output-names =
"reserved", "g_pclk_gpio1",
"g_pclk_gpio2", "g_pclk_gpio3",
"g_pclk_gpio4", "g_pclk_gpio5",
"g_pclk_gpio6", "g_pclk_gpio7",
"g_pclk_gpio8", "reserved",
"reserved", "g_pclk_grf",
"g_p_alive_niu", "reserved",
"reserved", "reserved";
//rockchip,suspend-clkgating-setting=<0xffff 0xffff>;
rockchip,suspend-clkgating-setting=<0x19fe 0x19fe>;
#clock-cells = <1>;
};
clk_gates15: gate-clk@019c {
compatible = "rockchip,rk3188-gate-clk";
reg = <0x019c 0x4>;
clocks =
<&aclk_rga>, <&hclk_vio>,
<&clk_gates15 11>, <&hclk_vio>,
<&dummy>, <&clk_gates15 11>,
<&hclk_vio>, <&clk_gates15 12>,
<&hclk_vio>, <&dummy>,
<&dummy>, <&aclk_vio0>,
<&aclk_vio1>, <&aclk_rga>,
<&clk_gates15 11>, <&hclk_vio>;
clock-output-names =
"reserved", /*"g_aclk_rga"*/ "g_hclk_rga",
"g_aclk_iep", "g_hclk_iep",
"g_aclk_lcdc_iep", "g_aclk_lcdc0",
"g_hclk_lcdc0", "g_aclk_lcdc1",
"g_hclk_lcdc1", "reserved", /* "g_h_vio_ahb" */
"reserved",/*"g_hclk_vio_niu"*/ "g_aclk_vio0_niu",
"g_aclk_vio1_niu", "reserved",/*"g_aclk_rga_niu"*/
"g_aclk_vip", "g_hclk_vip";
rockchip,suspend-clkgating-setting=<0x0 0x0>;
#clock-cells = <1>;
};
clk_gates16: gate-clk@01a0 {
compatible = "rockchip,rk3188-gate-clk";
reg = <0x01a0 0x4>;
clocks =
<&pclkin_cif>, <&hclk_vio>,
<&clk_gates15 12>, <&pclkin_isp>,
<&hclk_vio>, <&hclk_vio>,
<&hclk_vio>, <&hclk_vio>,
<&hclk_vio>, <&hclk_vio>,
<&dummy>, <&dummy>,
<&dummy>, <&dummy>,
<&dummy>, <&dummy>;
clock-output-names =
"g_pclkin_cif", "g_hclk_isp",
"g_aclk_isp", "g_pclkin_isp",
"g_p_mipi_dsi0", "g_p_mipi_dsi1",
"g_p_mipi_csi", "g_pclk_lvds_phy",
"g_pclk_edp_ctrl", "g_p_hdmi_ctrl",
"reserved", "reserved", /* bit10:"g_hclk_vio2_h2p" bit11: "g_pclk_vio2_h2p" */
"reserved", "reserved",
"reserved", "reserved";
rockchip,suspend-clkgating-setting=<0x0 0x0>;
#clock-cells = <1>;
};
clk_gates17: gate-clk@01a4 {
compatible = "rockchip,rk3188-gate-clk";
reg = <0x01a4 0x4>;
clocks =
<&pclk_pd_pmu>, <&pclk_pd_pmu>,
<&pclk_pd_pmu>, <&pclk_pd_pmu>,
<&pclk_pd_pmu>, <&dummy>,
<&dummy>, <&dummy>,
<&dummy>, <&dummy>,
<&dummy>, <&dummy>,
<&dummy>, <&dummy>,
<&dummy>, <&dummy>;
clock-output-names =
"g_pclk_pmu", "g_pclk_intmem1",
"g_pclk_pmu_niu", "g_pclk_sgrf",
"g_pclk_gpio0", "reserved",
"reserved", "reserved",
"reserved", "reserved",
"reserved", "reserved",
"reserved", "reserved",
"reserved", "reserved";
rockchip,suspend-clkgating-setting=<0x01f 0x01f>;
#clock-cells = <1>;
};
clk_gates18: gate-clk@01a8 {
compatible = "rockchip,rk3188-gate-clk";
reg = <0x01a8 0x4>;
clocks =
<&clk_gpu>, <&dummy>,
<&dummy>, <&dummy>,
<&dummy>, <&dummy>,
<&dummy>, <&dummy>,
<&dummy>, <&dummy>,
<&dummy>, <&dummy>,
<&dummy>, <&dummy>,
<&dummy>, <&dummy>;
clock-output-names =
"reserved", /*"g_aclk_gpu",*/ "reserved",
"reserved", "reserved",
"reserved", "reserved",
"reserved", "reserved",
"reserved", "reserved",
"reserved", "reserved",
"reserved", "reserved",
"reserved", "reserved";
rockchip,suspend-clkgating-setting=<0x0 0x0>;
#clock-cells = <1>;
};
};
};
};
};