关键词：rk3288-veyron-pinky.dts ,linux_3.10,rockchip,dts
dts — rk3288-veyron-pinky.dts
/*
* Google Veyron Pinky Rev 2 board device tree source
*
* Copyright 2015 Google, Inc
*
* This file is dual-licensed: you can use it either under the terms
* of the GPL or the X11 license, at your option. Note that this dual
* licensing only applies to this file, and not this project as a
* whole.
*
* a) This file is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
* published by the Free Software Foundation; either version 2 of the
* License, or (at your option) any later version.
*
* This file is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* Or, alternatively,
*
* b) Permission is hereby granted, free of charge, to any person
* obtaining a copy of this software and associated documentation
* files (the "Software"), to deal in the Software without
* restriction, including without limitation the rights to use,
* copy, modify, merge, publish, distribute, sublicense, and/or
* sell copies of the Software, and to permit persons to whom the
* Software is furnished to do so, subject to the following
* conditions:
*
* The above copyright notice and this permission notice shall be
* included in all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
* EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
* OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
* NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
* HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
* OTHER DEALINGS IN THE SOFTWARE.
*/
/dts-v1/;
#include "rk3288-veyron-chromebook.dtsi"
#include "cros-ec-sbs.dtsi"
/ {
model = "Google Pinky";
compatible = "google,veyron-pinky-rev2", "google,veyron-pinky",
"google,veyron", "rockchip,rk3288";
/delete-node/emmc-pwrseq;
};
&emmc {
/*
* Use a pullup instead of a drive since the output is 3.3V and
* really should be 1.8V (oops). The external pulldown will help
* bring the voltage down if we only drive with a pullup here.
* Therefore disable the powerseq (and actual reset) for pinky.
*/
/delete-property/mmc-pwrseq;
pinctrl-0 = <&emmc_clk &emmc_cmd &emmc_bus8 &emmc_reset>;
};
&gpio_keys {
pinctrl-0 = <&pwr_key_h &ap_lid_int_l>;
power {
gpios = <&gpio0 5 GPIO_ACTIVE_HIGH>;
};
};
/* Touchpad connector */
&i2c3 {
status = "okay";
clock-frequency = <400000>;
i2c-scl-falling-time-ns = <50>;
i2c-scl-rising-time-ns = <300>;
};
&pinctrl {
buttons {
pwr_key_h: pwr-key-h {
rockchip,pins = <0 5 RK_FUNC_GPIO &pcfg_pull_none>;
};
};
emmc {
emmc_reset: emmc-reset {
rockchip,pins = <7 12 RK_FUNC_GPIO &pcfg_pull_up>;
};
};
sdmmc {
sdmmc_wp_gpio: sdmmc-wp-gpio {
rockchip,pins = <7 10 RK_FUNC_GPIO &pcfg_pull_up>;
};
};
};
&rk808 {
regulators {
vcc18_lcd: SWITCH_REG2 {
regulator-always-on;
regulator-boot-on;
regulator-name = "vcc18_lcd";
regulator-state-mem {
regulator-off-in-suspend;
};
};
};
};
&sdmmc {
pinctrl-names = "default";
pinctrl-0 = <&sdmmc_clk &sdmmc_cmd &sdmmc_cd_disabled &sdmmc_cd_gpio
&sdmmc_wp_gpio &sdmmc_bus4>;
wp-gpios = <&gpio7 10 GPIO_ACTIVE_HIGH>;
};
&tsadc {
/* Some connection is flaky making the tsadc hang the system */
status = "disabled";
};
max-frequency = <150000000>;
mmc-pwrseq = <&sdio_pwrseq>;
num-slots = <1>;
sd-uhs-sdr104;
status = "okay";
};
&sdmmc {
bus-width = <4>;
cap-mmc-highspeed;
cap-sd-highspeed;
card-detect-delay = <200>;
disable-wp;
max-frequency = <50000000>;
num-slots = <1>;
supports-sd;
vmmc-supply = <&vcc_sd>;
pinctrl-names = "default";
pinctrl-0 = <&sdmmc_clk &sdmmc_cmd &sdmmc_bus4 &sdmmc_cd>;
status = "okay";
};
&vop {
assigned-clocks = <&cru DCLK_VOP>;
assigned-clock-parents = <&cru HDMIPHY>;
status = "okay";
};
&vop_mmu {
status = "okay";
};
VALUE_PULL_DOWN>;
};
//to add
};
gpio7_gpio {
gpio7_b7: gpio7-b7 {
rockchip,pins = <GPIO7_B7>;
rockchip,pull = <VALUE_PULL_UP>;
};
//to add
};
//could add other pinctrl definition such as gpio
// gmac drive strength
gpio4_gmac {
mac_clk: mac-clk {
rockchip,drive = <VALUE_DRV_12MA>;
};
mac_txpins: mac-txpins {
rockchip,drive = <VALUE_DRV_12MA>;
};
mac_rxpins: mac-rxpins {
rockchip,drive = <VALUE_DRV_12MA>;
};
mac_crs: mac-crs {
rockchip,drive = <VALUE_DRV_12MA>;
};
mac_mdpins: mac-mdpins {
rockchip,drive = <VALUE_DRV_12MA>;
};
};
};
&nandc0 {
status = "okay"; // used nand set "okay" ,used emmc set "disabled"
};
&nandc1 {
status = "disabled"; // used nand set "okay" ,used emmc set "disabled"
};
&nandc0reg {
status = "disabled"; // used nand set "okay" ,used emmc set "disabled"
};
&emmc {
clock-frequency = <100000000>;
clock-freq-min-max = <400000 100000000>;
supports-highspeed;
supports-emmc;
bootpart-no-access;
supports-tSD;//only tsd-sdcard mode
supports-DDR_MODE;
caps2-mmc-hs200;
ignore-pm-notify;
keep-power-in-suspend;
//poll-hw-reset
status = "okay";
};
&sdmmc {
clock-frequency = <50000000>;
lock-freq-min-max = <400000 50000000>;
supports-highspeed;
supports-sd;
broken-cd;
card-detect-delay = <200>;
ignore-pm-notify;
keep-power-in-suspend;
vmmc-supply = <&ldo1_reg>;
status = "okay";
};
&sdio {
clock-frequency = <50000000>;
clock-freq-min-max = <200000 50000000>;
supports-highspeed;
supports-sdio;
ignore-pm-notify;
keep-power-in-suspend;
//cap-sdio-irq;
status = "okay";
};
&spi0 {
status = "disabled";
max-freq = <48000000>;
/*
spi_test@00 {
compatible = "rockchip,spi_test_bus0_cs0";
reg = <0>;
spi-max-frequency = <24000000>;
//spi-cpha;
//spi-cpol;
poll_mode = <0>;
type = <0>;
enable_dma = <0>;
};
spi_test@01 {
compatible = "rockchip,spi_test_bus0_cs1";
reg = <1>;
spi-max-frequency = <24000000>;
spi-cpha;
spi-cpol;
poll_mode = <0>;
type = <0>;
enable_dma = <0>;
};
*/
};
&spi1 {
status = "disabled";
max-freq = <48000000>;
/*
spi_test@10 {
compatible = "rockchip,spi_test_bus1_cs0";
reg = <0>;
spi-max-frequency = <24000000>;
//spi-cpha;
//spi-cpol;
poll_mode = <0>;
type = <0>;
enable_dma = <0>;
};
*/
//dtv: connect to dtv demodulator for control signal
tstv-ctrl@00 {
compatible = "rockchip,dtv_spi_ctrl";
gpio-powerup = <&gpio0 GPIO_D7 GPIO_ACTIVE_HIGH>;
gpio-powerdown = <&gpio2 GPIO_B6 GPIO_ACTIVE_HIGH>;
gpio-reset = <&gpio2 GPIO_B7 GPIO_ACTIVE_HIGH>;
gpio-nreset = <&gpio2 GPIO_B4 GPIO_ACTIVE_HIGH>;
spi-max-frequency = <12000000>;
reg = <0>;
poll_mode = <0>;
type = <0>;
enable_dma = <0>;
};
};
&spi2 {
status = "disabled";
max-freq = <48000000>;
/*
spi_test@20 {
compatible = "rockchip,spi_test_bus2_cs0";
reg = <0>;
spi-max-frequency = <24000000>;
//spi-cpha;
//spi-cpol;
poll_mode = <0>;
type = <0>;
enable_dma = <0>;
};
spi_test@21 {
compatible = "rockchip,spi_test_bus2_cs1";
reg = <1>;
spi-max-frequency = <24000000>;
//spi-cpha;
//spi-cpol;
poll_mode = <0>;
type = <0>;
enable_dma = <0>;
};
*/
};
&uart_bt {
status = "okay";
dma-names = "!tx", "!rx";
pinctrl-0 = <&uart0_xfer &uart0_cts>;
};
&i2c0 {
status = "okay";
rk808: rk808@1b {
reg = <0x1b>;
status = "okay";
};
syr827: syr827@40 {
compatible = "silergy,syr82x";
reg = <0x40>;
status = "okay";
regulators {
#address-cells = <1>;
#size-cells = <0>;
syr827_dc1: regulator@0 {
reg = <0>;
regulator-compatible = "syr82x_dcdc1";
regulator-name = "vdd_arm";
regulator-min-microvolt = <712500>;
regulator-max-microvolt = <1500000>;
regulator-always-on;
regulator-boot-on;
regulator-initial-mode = <0x2>;
regulator-initial-state = <3>;
regulator-state-mem {
regulator-state-mode = <0x2>;
regulator-state-enabled;
regulator-state-uv = <900000>;
};
};
};
};
syr828: syr828@41 {
compatible = "silergy,syr82x";
reg = <0x41>;
status = "okay";
regulators {
#address-cells = <1>;
#size-cells = <0>;
syr828_dc1: regulator@0 {
reg = <0>;
regulator-compatible = "syr82x_dcdc1";
regulator-name = "vdd_gpu";
regulator-min-microvolt = <712500>;
regulator-max-microvolt = <1500000>;
regulator-always-on;
regulator-boot-on;
regulator-initial-mode = <0x2>;
regulator-initial-state = <3>;
regulator-state-mem {
regulator-state-mode = <0x2>;
regulator-state-disabled;
regulator-state-uv = <900000>;
};
};
};
};
act8846: act8846@5a {
reg = <0x5a>;
status = "okay";
};
rtc@51 {
compatible = "rtc,hym8563";
reg = <0x51>;
irq_gpio = <&gpio0 GPIO_A4 IRQ_TYPE_EDGE_FALLING>;
};
};
&i2c1 {
status = "okay";
rtc@51 {
compatible = "nxp,pcf8563";
reg = <0x51>;
};
};
&i2c2 {
status = "okay";
};
&i2c3 {
status = "okay";
};
&i2c4 {
status = "okay";
rk1000_control@40 {
compatible = "rockchip,rk1000_control";
reg = <0x40>;
gpio-reset = <&gpio7 GPIO_C5 GPIO_ACTIVE_LOW>;
#clocks = <&clk_i2s>, <&clk_i2s_out>;
#clock-names = "i2s_clk","i2s_mclk";
#pinctrl-names = "default";
#pinctrl-0 = <&i2s_mclk>;
status = "okay";
};
rk1000_tve@42 {
compatible = "rockchip,rk1000_tve";
reg = <0x42>;
rockchip,source = <0>; //0: LCDC0; 1: LCDC1
rockchip,prop = <PRMRY>;//<EXTEND>
status = "okay";
};
rk1000_codec: rk1000_codec@60 {
compatible = "rockchip,rk1000_codec";
reg = <0x60>;
spk_ctl_io = <&gpio7 GPIO_A5 GPIO_ACTIVE_LOW>;
boot_depop = <1>;
pa_enable_time = <5000>;
status = "okay";
};
};
&i2c5 {
status = "disabled";
};
&fb {
rockchip,disp-mode = <NO_DUAL>;
rockchip,uboot-logo-on = <1>;
rockchip,disp-policy = <DISPLAY_POLICY_BOX>;
};
&disp_timings {
native-mode = <&timing1>;
};
&rk_screen {
display-timings = <&disp_timings>;
};
/*lcdc0 as PRMRY(HDMI)*/
&lcdc0 {
status = "okay";
rockchip,iommu-enabled = <1>;
rockchip,prop = <PRMRY>;
};
&lcdc1 {
status = "disabled";
rockchip,iommu-enabled = <1>;
rockchip,prop = <EXTEND>;
};
&hdmi {
status = "okay";
rockchip,cec_enable = <0>;
rockchip,hdcp_enable = <0>;
};
&ion_cma {
reg = <0x00000000 0x1000000>; /* 16MB */
};
&vpu {
iommu_enabled = <1>;
};
&hevc {
iommu_enabled = <1>;
};
&iep {
iommu_enabled = <1>;
};
&adc {
status = "disabled";
key {
compatible = "rockchip,key";
/*
io-channels = <&adc 1>;
vol-up-key {
linux,code = <115>;
label = "volume up";
rockchip,adc_value = <1>;
};
vol-down-key {
linux,code = <114>;
label = "volume down";
rockchip,adc_value = <170>;
};
*/
power-key {
gpios = <&gpio0 GPIO_A5 GPIO_ACTIVE_LOW>;
linux,code = <116>;
label = "power";
gpio-key,wakeup;
};
/*
menu-key {
linux,code = <59>;
label = "menu";
rockchip,adc_value = <355>;
};
home-key {
linux,code = <102>;
label = "home";
rockchip,adc_value = <746>;
};
back-key {
linux,code = <158>;
label = "back";
rockchip,adc_value = <560>;
};
camera-key {
linux,code = <212>;
label = "camera";
rockchip,adc_value = <450>;
};*/
};
};
&pwm1 {
status = "disabled";
};
&clk_core_dvfs_table {
support-pvtm = <1>;
pvtm-operating-points = <
/* KHz uV pvtm margin*/
// 126000 900000 25000
// 216000 900000 25000
// 312000 900000 25000
408000 900000 25000
600000 950000 50000
696000 950000 50000
816000 1000000 50000
1008000 1050000 75000
1200000 1100000 75000
1416000 1200000 75000
1512000 1300000 75000
1608000 1350000 75000
// 1704000 1350000 75000
// 1800000 1350000 75000
>;
status="okay";
};
&clk_gpu_dvfs_table {
operating-points = <
/* KHz uV */
// 100000 900000
200000 900000
300000 950000
420000 1100000
500000 1150000
// 600000 1250000
>;
status="okay";
};
&clk_ddr_dvfs_table {
operating-points = <
/* KHz uV */
200000 1075000
300000 1075000
456000 1125000
533000 1150000
>;
freq-table = <
/*status freq(KHz)*/
SYS_STATUS_NORMAL 456000
SYS_STATUS_SUSPEND 200000
//SYS_STATUS_VIDEO_1080P 240000
SYS_STATUS_VIDEO_4K 533000
SYS_STATUS_PERFORMANCE 533000
//SYS_STATUS_BOOST 324000
//SYS_STATUS_ISP 400000
>;
auto-freq-table = <
240000
324000
456000
528000
>;
auto-freq=<0>;
status="okay";
};
/include/ "act8846.dtsi"
&act8846 {
gpios =<&gpio7 GPIO_A1 GPIO_ACTIVE_LOW>,<&gpio0 GPIO_B2 GPIO_ACTIVE_HIGH>;
act8846,system-power-controller;
regulators {
dcdc1_reg: regulator@0{
regulator-name= "act_dcdc1";
regulator-min-microvolt = <1200000>;
regulator-max-microvolt = <1200000>;
regulator-always-on;
regulator-boot-on;
};
dcdc2_reg: regulator@1 {
regulator-name= "vccio";
regulator-min-microvolt = <3300000>;
regulator-max-microvolt = <3300000>;
regulator-initial-state = <3>;
regulator-state-mem {
regulator-state-enabled;
regulator-state-uv = <3300000>;
};
};
dcdc3_reg: regulator@2 {
regulator-name= "vdd_logic";
regulator-min-microvolt = <700000>;
regulator-max-microvolt = <1500000>;
regulator-initial-state = <3>;
regulator-state-mem {
regulator-state-enabled;
regulator-state-uv = <1200000>;
};
};
dcdc4_reg: regulator@3 {
regulator-name= "act_dcdc4";
regulator-min-microvolt = <2000000>;
regulator-max-microvolt = <2000000>;
regulator-initial-state = <3>;
regulator-state-mem {
regulator-state-enabled;
regulator-state-uv = <2000000>;
};
};
ldo1_reg: regulator@4 {
regulator-name= "vccio_sd";
regulator-min-microvolt = <1800000>;
regulator-max-microvolt = <3300000>;
};
ldo2_reg: regulator@5 {
regulator-name= "act_ldo2";
regulator-min-microvolt = <1050000>;
regulator-max-microvolt = <1050000>;
};
ldo3_reg: regulator@6 {
regulator-name= "act_ldo3";
regulator-min-microvolt = <1800000>;
regulator-max-microvolt = <1800000>;
};
ldo4_reg:regulator@7 {
regulator-name= "act_ldo4";
regulator-min-microvolt = <3300000>;
regulator-max-microvolt = <3300000>;
};
ldo5_reg: regulator@8 {
regulator-name= "act_ldo5";
regulator-min-microvolt = <3300000>;
regulator-max-microvolt = <3300000>;
};
ldo6_reg: regulator@9 {
regulator-name= "act_ldo6";
regulator-min-microvolt = <1100000>;
regulator-max-microvolt = <1100000>;
regulator-initial-state = <3>;
regulator-state-mem {
regulator-state-enabled;
};
};
ldo7_reg: regulator@10 {
regulator-name= "vcc_18";
regulator-min-microvolt = <1800000>;
regulator-max-microvolt = <1800000>;
regulator-initial-state = <3>;
regulator-state-mem {
regulator-state-enabled;
};
};
ldo8_reg: regulator@11 {
regulator-name= "act_ldo8";
regulator-min-microvolt = <1850000>;
regulator-max-microvolt = <1850000>;
};
};
};
/include/ "rk808.dtsi"
&rk808 {
gpios =<&gpio0 GPIO_A4 GPIO_ACTIVE_HIGH>,<&gpio0 GPIO_B3 GPIO_ACTIVE_LOW>;
rk808,system-power-controller;
regulators {
rk808_dcdc1_reg: regulator@0{
regulator-name= "vdd_arm";
regulator-min-microvolt = <700000>;
regulator-max-microvolt = <1500000>;
regulator-always-on;
regulator-boot-on;
regulator-initial-mode = <0x2>;
regulator-initial-state = <3>;
regulator-state-mem {
regulator-state-mode = <0x2>;
regulator-state-disabled;
regulator-state-uv = <900000>;
};
};
rk808_dcdc2_reg: regulator@1 {
regulator-name= "vdd_gpu";
regulator-min-microvolt = <700000>;
regulator-max-microvolt = <1500000>;
regulator-always-on;
regulator-boot-on;
regulator-initial-mode = <0x2>;
regulator-initial-state = <3>;
regulator-state-mem {
regulator-state-mode = <0x2>;
regulator-state-disabled;
regulator-state-uv = <900000>;
};
};
rk808_dcdc3_reg: regulator@2 {
regulator-name= "rk_dcdc3";
regulator-min-microvolt = <1200000>;
regulator-max-microvolt = <1200000>;
regulator-always-on;
regulator-boot-on;
regulator-initial-mode = <0x2>;
regulator-initial-state = <3>;
regulator-state-mem {
regulator-state-mode = <0x2>;
regulator-state-enabled;
regulator-state-uv = <1200000>;
};
};
rk808_dcdc4_reg: regulator@3 {
regulator-name= "vccio";
regulator-min-microvolt = <1800000>;
regulator-max-microvolt = <3300000>;
regulator-always-on;
regulator-boot-on;
regulator-initial-mode = <0x2>;
regulator-initial-state = <3>;
regulator-state-mem {
regulator-state-mode = <0x2>;
regulator-state-enabled;
regulator-state-uv = <2800000>;
};
};
/* NO USED, 3.3V*/
rk808_ldo1_reg: regulator@4 {
regulator-name= "rk_ldo1";
regulator-min-microvolt = <3300000>;
regulator-max-microvolt = <3300000>;
regulator-always-on;
regulator-boot-on;
regulator-initial-state = <3>;
regulator-state-mem {
regulator-state-enabled;
regulator-state-uv = <3300000>;
};
};
/* BOX:RK1000s, 3.3V */
rk808_ldo2_reg: regulator@5 {
regulator-name= "rk_ldo2";
regulator-min-microvolt = <3300000>;
regulator-max-microvolt = <3300000>;
regulator-always-on;
regulator-boot-on;
regulator-initial-state = <3>;
regulator-state-mem {
regulator-state-enabled;
regulator-state-uv = <3300000>;
};
};
/* RK3288 PLL,USB PHY, 1.0V */
rk808_ldo3_reg: regulator@6 {
regulator-name= "rk_ldo3";
regulator-min-microvolt = <1000000>;
regulator-max-microvolt = <1000000>;
regulator-always-on;
regulator-boot-on;
regulator-initial-state = <3>;
regulator-state-mem {
regulator-state-enabled;
regulator-state-uv = <1000000>;
};
};
/* BOX:RK1000S CORE, 1.8V */
rk808_ldo4_reg:regulator@7 {
regulator-name= "rk_ldo4";
regulator-min-microvolt = <1800000>;
regulator-max-microvolt = <1800000>;
regulator-always-on;
regulator-boot-on;
regulator-initial-state = <3>;
regulator-state-mem {
regulator-state-disabled;
regulator-state-uv = <1800000>;
};
};
/* SDMMC IO, 3.3V*/
rk808_ldo5_reg: regulator@8 {
regulator-name= "rk_ldo5";
regulator-min-microvolt = <3300000>;
regulator-max-microvolt = <3300000>;
regulator-always-on;
regulator-boot-on;
regulator-initial-state = <3>;
regulator-state-mem {
regulator-state-enabled;
regulator-state-uv = <3300000>;
};
};
/* CAMERA, 1.8V box modify*/
rk808_ldo6_reg: regulator@9 {
regulator-name= "rk_ldo6";
regulator-min-microvolt = <1800000>;
regulator-max-microvolt = <1800000>;
regulator-always-on;
regulator-boot-on;
regulator-initial-state = <3>;
regulator-state-mem {
regulator-state-disabled;
regulator-state-uv = <1000000>;
};
};
/* RK3288 USB PHY, SAR-ADC, WIFI IO, 1.8V */
rk808_ldo7_reg: regulator@10 {
regulator-name= "rk_ldo7";
regulator-min-microvolt = <1800000>;
regulator-max-microvolt = <1800000>;
regulator-always-on;
regulator-boot-on;
regulator-initial-state = <3>;
regulator-state-mem {
regulator-state-enabled;
regulator-state-uv = <1800000>;
};
};
/* DTV, 3.3V box modify*/
rk808_ldo8_reg: regulator@11 {
regulator-name= "rk_ldo8";
regulator-min-microvolt = <3300000>;
regulator-max-microvolt = <3300000>;
regulator-always-on;
regulator-boot-on;
regulator-initial-state = <3>;
regulator-state-mem {
regulator-state-enabled;
regulator-state-uv = <3300000>;
};
};
rk808_ldo9_reg: regulator@12 {
regulator-name= "rk_ldo9";
regulator-always-on;
regulator-boot-on;
regulator-initial-state = <3>;
regulator-state-mem {
regulator-state-enabled;
};
};
rk808_ldo10_reg: regulator@13 {
regulator-name= "rk_ldo10";
regulator-always-on;
regulator-boot-on;
regulator-initial-state = <3>;
regulator-state-mem {
regulator-state-disabled;
};
};
};
};
&lcdc_vdd_domain {
regulator-name = "vcc30_lcd";
};
&dpio_vdd_domain{
regulator-name = "vcc18_cif";
};
&flash0_vdd_domain{
regulator-name = "vcc_flash";
};
&flash1_vdd_domain{
regulator-name = "vcc_flash";
};
&apio3_vdd_domain{
regulator-name = "vccio_wl";
};
&apio5_vdd_domain{
regulator-name = "vccio";
};
&apio4_vdd_domain{
regulator-name = "vccio";
};
&apio1_vdd_domain{
regulator-name = "vccio";
};
&apio2_vdd_domain{
regulator-name = "vccio";
};
&sdmmc0_vdd_domain{
regulator-name = "vcc_sd";
};
/*
* Due to not have the software of PWM for remotectrl.
* We can _*HACK*_ do that as the following.
*/
&pwm0 {
compatible = "rockchip,remotectl-pwm";
remote_pwm_id = <0>;
handle_cpu_id = <1>;
status = "okay";
ir_key1{
rockchip,usercode = <0x4040>;
rockchip,key_table =
<0xf2 KEY_REPLY>,
<0xba KEY_BACK>,
<0xf4 KEY_UP>,
<0xf1 KEY_DOWN>,
<0xef KEY_LEFT>,
<0xee KEY_RIGHT>,
<0xbd KEY_HOME>,
<0xea KEY_VOLUMEUP>,
<0xe3 KEY_VOLUMEDOWN>,
<0xe2 KEY_SEARCH>,
<0xb2 KEY_POWER>,
<0xbc KEY_MUTE>,
<0xec KEY_MENU>,
<0xbf 0x190>,
<0xe0 0x191>,
<0xe1 0x192>,
<0xe9 183>,
<0xe6 248>,
<0xe8 185>,
<0xe7 186>,
<0xf0 388>,
<0xbe 0x175>;
};
ir_key2{
rockchip,usercode = <0xff00>;
rockchip,key_table =
<0xf9 KEY_HOME>,
<0xbf KEY_BACK>,
<0xfb KEY_MENU>,
<0xaa KEY_REPLY>,
<0xb9 KEY_UP>,
<0xe9 KEY_DOWN>,
<0xb8 KEY_LEFT>,
<0xea KEY_RIGHT>,
<0xeb KEY_VOLUMEDOWN>,
<0xef KEY_VOLUMEUP>,
<0xf7 KEY_MUTE>,
<0xe7 KEY_POWER>,
<0xfc KEY_POWER>,
<0xa9 KEY_VOLUMEDOWN>,
<0xa8 KEY_VOLUMEDOWN>,
<0xe0 KEY_VOLUMEDOWN>,
<0xa5 KEY_VOLUMEDOWN>,
<0xab 183>,
<0xb7 388>,
<0xf8 184>,
<0xaf 185>,
<0xed KEY_VOLUMEDOWN>,
<0xee 186>,
<0xb3 KEY_VOLUMEDOWN>,
<0xf1 KEY_VOLUMEDOWN>,
<0xf2 KEY_VOLUMEDOWN>,
<0xf3 KEY_SEARCH>,
<0xb4 KEY_VOLUMEDOWN>,
<0xbe KEY_SEARCH>;
};
ir_key3{
rockchip,usercode = <0x1dcc>;
rockchip,key_table =
<0xee KEY_REPLY>,
<0xf0 KEY_BACK>,
<0xf8 KEY_UP>,
<0xbb KEY_DOWN>,
<0xef KEY_LEFT>,
<0xed KEY_RIGHT>,
<0xfc KEY_HOME>,
<0xf1 KEY_VOLUMEUP>,
<0xfd KEY_VOLUMEDOWN>,
<0xb7 KEY_SEARCH>,
<0xff KEY_POWER>,
<0xf3 KEY_MUTE>,
<0xbf KEY_MENU>,
<0xf9 0x191>,
<0xf5 0x192>,
<0xb3 388>,
<0xbe KEY_1>,
<0xba KEY_2>,
<0xb2 KEY_3>,
<0xbd KEY_4>,
<0xf9 KEY_5>,
<0xb1 KEY_6>,
<0xfc KEY_7>,
<0xf8 KEY_8>,
<0xb0 KEY_9>,
<0xb6 KEY_0>,
<0xb5 KEY_BACKSPACE>;
};
};
#clock-cells = <0>;
};
};
clk_sel_con12: sel-con@0090 {
compatible = "rockchip,rk3188-selcon";
reg = <0x0090 0x4>;
#address-cells = <1>;
#size-cells = <1>;
clk_sdio0_div: clk_sdio0_div {
compatible = "rockchip,rk3188-div-con";
rockchip,bits = <0 6>;
clocks = <&clk_sdio0>;
clock-output-names = "clk_sdio0";
rockchip,div-type = <CLK_DIVIDER_PLUS_ONE>;
#clock-cells = <0>;
rockchip,clkops-idx =
<CLKOPS_RATE_MUX_EVENDIV>;
};
clk_sdio0: clk_sdio0_mux {
compatible = "rockchip,rk3188-mux-con";
rockchip,bits = <6 2>;
clocks = <&dummy_cpll>, <&clk_gpll>, <&xin24m>;
clock-output-names = "clk_sdio0";
#clock-cells = <0>;
};
clk_emmc_div: clk_emmc_div {
compatible = "rockchip,rk3188-div-con";
rockchip,bits = <8 6>;
clocks = <&clk_emmc>;
clock-output-names = "clk_emmc";
rockchip,div-type = <CLK_DIVIDER_PLUS_ONE>;
#clock-cells = <0>;
rockchip,clkops-idx =
<CLKOPS_RATE_MUX_EVENDIV>;
};
clk_emmc: clk_emmc_mux {
compatible = "rockchip,rk3188-mux-con";
rockchip,bits = <14 2>;
clocks = <&dummy_cpll>, <&clk_gpll>, <&xin24m>;
clock-output-names = "clk_emmc";
#clock-cells = <0>;
};
};
clk_sel_con13: sel-con@0094 {
compatible = "rockchip,rk3188-selcon";
reg = <0x0094 0x4>;
#address-cells = <1>;
#size-cells = <1>;
clk_uart0_pll_div: clk_uart0_pll_div {
compatible = "rockchip,rk3188-div-con";
rockchip,bits = <0 7>;
clocks = <&clk_uart0_pll>;
clock-output-names = "clk_uart0_pll";
rockchip,div-type = <CLK_DIVIDER_PLUS_ONE>;
#clock-cells = <0>;
rockchip,clkops-idx =
<CLKOPS_RATE_MUX_DIV>;
};
/* reg[7]: reserved */
clk_uart0: uart0_mux {
compatible = "rockchip,rk3188-mux-con";
rockchip,bits = <8 2>;
clocks = <&clk_uart0_pll>, <&uart0_frac>, <&xin24m>, <&dummy>;
clock-output-names = "clk_uart0";
#clock-cells = <0>;
rockchip,clkops-idx =
<CLKOPS_RATE_RK3288_I2S>;
rockchip,flags = <CLK_SET_RATE_PARENT>;
};
/* reg[10]: reserved */
usbphy_480m: usbphy_480m_mux {
compatible = "rockchip,rk3188-mux-con";
rockchip,bits = <11 2>;
clocks = <&otgphy1_480m>, <&otgphy2_480m>, <&otgphy0_480m>;
clock-output-names = "usbphy_480m";
#clock-cells = <0>;
rockchip,clkops-idx =
<CLKOPS_RATE_RK3288_USB480M>;
#clock-init-cells = <1>;
};
clk_uart0_pll: clk_uart0_pll_mux {
compatible = "rockchip,rk3188-mux-con";
rockchip,bits = <13 2>;
clocks = <&dummy_cpll>, <&clk_gpll>, <&usbphy_480m>, <&clk_npll>;
clock-output-names = "clk_uart0_pll";
#clock-cells = <0>;
};
uart_pll_mux: uart_pll_mux {
compatible = "rockchip,rk3188-mux-con";
rockchip,bits = <15 1>;
clocks = <&dummy_cpll>, <&clk_gpll>;
clock-output-names = "uart_pll_mux";
#clock-cells = <0>;
#clock-init-cells = <1>;
};
};
clk_sel_con14: sel-con@0098 {
compatible = "rockchip,rk3188-selcon";
reg = <0x0098 0x4>;
#address-cells = <1>;
#size-cells = <1>;
clk_uart1_div: clk_uart1_div {
compatible = "rockchip,rk3188-div-con";
rockchip,bits = <0 7>;
clocks = <&uart_pll_mux>;
clock-output-names = "clk_uart1_div";
rockchip,div-type = <CLK_DIVIDER_PLUS_ONE>;
#clock-cells = <0>;
};
/* reg[7]: reserved */
clk_uart1: uart1_mux {
compatible = "rockchip,rk3188-mux-con";
rockchip,bits = <8 2>;
clocks = <&clk_uart1_div>, <&uart1_frac>, <&xin24m>, <&dummy>;
clock-output-names = "clk_uart1";
#clock-cells = <0>;
rockchip,clkops-idx =
<CLKOPS_RATE_RK3288_I2S>;
rockchip,flags = <CLK_SET_RATE_PARENT>;
};
/* reg[15:10]: reserved */
};
clk_sel_con15: sel-con@009c {
compatible = "rockchip,rk3188-selcon";
reg = <0x009c 0x4>;
#address-cells = <1>;
#size-cells = <1>;
clk_uart2_div: clk_uart2_div {
compatible = "rockchip,rk3188-div-con";
rockchip,bits = <0 7>;
clocks = <&uart_pll_mux>;
clock-output-names = "clk_uart2_div";
rockchip,div-type = <CLK_DIVIDER_PLUS_ONE>;
#clock-cells = <0>;
};
/* reg[7]: reserved */
clk_uart2: uart2_mux {
compatible = "rockchip,rk3188-mux-con";
rockchip,bits = <8 2>;
clocks = <&clk_uart2_div>, <&uart2_frac>, <&xin24m>, <&dummy>;
clock-output-names = "clk_uart2";
#clock-cells = <0>;
rockchip,clkops-idx =
<CLKOPS_RATE_RK3288_I2S>;
rockchip,flags = <CLK_SET_RATE_PARENT>;
};
/* reg[15:10]: reserved */
};
clk_sel_con16: sel-con@00a0 {
compatible = "rockchip,rk3188-selcon";
reg = <0x00a0 0x4>;
#address-cells = <1>;
#size-cells = <1>;
clk_uart3_div: clk_uart3_div {
compatible = "rockchip,rk3188-div-con";
rockchip,bits = <0 7>;
clocks = <&uart_pll_mux>;
clock-output-names = "clk_uart3_div";
rockchip,div-type = <CLK_DIVIDER_PLUS_ONE>;
#clock-cells = <0>;
};
/* reg[7]: reserved */
clk_uart3: uart3_mux {
compatible = "rockchip,rk3188-mux-con";
rockchip,bits = <8 2>;
clocks = <&clk_uart3_div>, <&uart3_frac>, <&xin24m>, <&dummy>;
clock-output-names = "clk_uart3";
#clock-cells = <0>;
rockchip,clkops-idx =
<CLKOPS_RATE_RK3288_I2S>;
rockchip,flags = <CLK_SET_RATE_PARENT>;
};
/* reg[15:10]: reserved */
};
clk_sel_con17: sel-con@00a4 {
compatible = "rockchip,rk3188-selcon";
reg = <0x00a4 0x4>;
#address-cells = <1>;
#size-cells = <1>;
uart0_frac: uart0_frac {
compatible = "rockchip,rk3188-frac-con";
clocks = <&clk_uart0_pll>;
clock-output-names = "uart0_frac";
/* numerator denominator */
rockchip,bits = <0 32>;
rockchip,clkops-idx =
<CLKOPS_RATE_FRAC>;
#clock-cells = <0>;
};
};
clk_sel_con18: sel-con@00a8 {
compatible = "rockchip,rk3188-selcon";
reg = <0x00a8 0x4>;
#address-cells = <1>;
#size-cells = <1>;
uart1_frac: uart1_frac {
compatible = "rockchip,rk3188-frac-con";
clocks = <&clk_uart1_div>;
clock-output-names = "uart1_frac";
/* numerator denominator */
rockchip,bits = <0 32>;
rockchip,clkops-idx =
<CLKOPS_RATE_FRAC>;
#clock-cells = <0>;
};
};
clk_sel_con19: sel-con@00ac {
compatible = "rockchip,rk3188-selcon";
reg = <0x00ac 0x4>;
#address-cells = <1>;
#size-cells = <1>;
uart2_frac: uart2_frac {
compatible = "rockchip,rk3188-frac-con";
clocks = <&clk_uart2_div>;
clock-output-names = "uart2_frac";
/* numerator denominator */
rockchip,bits = <0 32>;
rockchip,clkops-idx =
<CLKOPS_RATE_FRAC>;
#clock-cells = <0>;
};
};
clk_sel_con20: sel-con@00b0 {
compatible = "rockchip,rk3188-selcon";
reg = <0x00b0 0x4>;
#address-cells = <1>;
#size-cells = <1>;
uart3_frac: uart3_frac {
compatible = "rockchip,rk3188-frac-con";
clocks = <&clk_uart3_div>;
clock-output-names = "uart3_frac";
/* numerator denominator */
rockchip,bits = <0 32>;
rockchip,clkops-idx =
<CLKOPS_RATE_FRAC>;
#clock-cells = <0>;
};
};
clk_sel_con21: sel-con@00b4 {
compatible = "rockchip,rk3188-selcon";
reg = <0x00b4 0x4>;
#address-cells = <1>;
#size-cells = <1>;
clk_mac_pll: clk_mac_pll_mux {
compatible = "rockchip,rk3188-mux-con";
rockchip,bits = <0 2>;
clocks = <&clk_npll>, <&dummy_cpll>, <&clk_gpll>;
clock-output-names = "clk_mac_pll";
#clock-cells = <0>;
};
/* reg[3:2]: reserved */
clk_mac: clk_mac_mux {
compatible = "rockchip,rk3188-mux-con";
rockchip,bits = <4 1>;
clocks = <&clk_mac_pll>, <&gmac_clkin>;
clock-output-names = "clk_mac";
#clock-cells = <0>;
rockchip,clkops-idx =
<CLKOPS_RATE_MAC_REF>;
rockchip,flags = <CLK_SET_RATE_PARENT>;
#clock-init-cells = <1>;
};
/* reg[7:5]: reserved */
clk_mac_pll_div: clk_mac_pll_div {
compatible = "rockchip,rk3188-div-con";
rockchip,bits = <8 5>;
clocks = <&clk_mac_pll>;
clock-output-names = "clk_mac_pll";
rockchip,div-type = <CLK_DIVIDER_PLUS_ONE>;
#clock-cells = <0>;
rockchip,clkops-idx =
<CLKOPS_RATE_MUX_DIV>;
};
/* reg[15:13]: reserved */
};
clk_sel_con22: sel-con@00b8 {
compatible = "rockchip,rk3188-selcon";
reg = <0x00b8 0x4>;
#address-cells = <1>;
#size-cells = <1>;
clk_hsadc_pll: clk_hsadc_pll_mux {
compatible = "rockchip,rk3188-mux-con";
rockchip,bits = <0 1>;
clocks = <&dummy_cpll>, <&clk_gpll>;
clock-output-names = "clk_hsadc_pll";
#clock-cells = <0>;
};
/*
wifi_pll_mux: wifi_pll_mux {
compatible = "rockchip,rk3188-mux-con";
rockchip,bits = <1 1>;
clocks = <&>, <&>;
clock-output-names = "wifi_pll_mux";
#clock-cells = <0>;
};
*/
/* reg[3:2]: reserved */
clk_hsadc_out: clk_hsadc_out {
compatible = "rockchip,rk3188-mux-con";
rockchip,bits = <4 1>;
clocks = <&clk_hsadc_pll>, <&clk_hsadc_ext>;
clock-output-names = "clk_hsadc_out";
#clock-cells = <0>;
rockchip,clkops-idx =
<CLKOPS_RATE_HSADC>;
rockchip,flags = <CLK_SET_RATE_PARENT>;
};
/* reg[6:5]: reserved */
clk_hsadc: clk_hsadc {
compatible = "rockchip,rk3188-mux-con";
rockchip,bits = <7 1>;
clocks = <&clk_hsadc_out>, <&clk_hsadc_inv>;
clock-output-names = "clk_hsadc";
#clock-cells = <0>;
};
clk_hsadc_pll_div: clk_hsadc_pll_div {
compatible = "rockchip,rk3188-div-con";
rockchip,bits = <8 8>;
clocks = <&clk_hsadc_pll>;
clock-output-names = "clk_hsadc_pll";
rockchip,div-type = <CLK_DIVIDER_PLUS_ONE>;
#clock-cells = <0>;
rockchip,clkops-idx =
<CLKOPS_RATE_MUX_DIV>;
};
};
/*
clk_sel_con23: sel-con@00bc {
compatible = "rockchip,rk3188-selcon";
reg = <0x00bc 0x4>;
#address-cells = <1>;
#size-cells = <1>;
wifi_frac: wifi_frac {
compatible = "rockchip,rk3188-frac-con";
clocks = <&>;
clock-output-names = "wifi_frac";
/ numerator denominator /
rockchip,bits = <0 32>;
rockchip,clkops-idx =
<>;
#clock-cells = <0>;
};
};
*/
clk_sel_con24: sel-con@00c0 {
compatible = "rockchip,rk3188-selcon";
reg = <0x00c0 0x4>;
#address-cells = <1>;
#size-cells = <1>;
/* reg[7:0]: reserved */
clk_saradc: clk_saradc_div {
compatible = "rockchip,rk3188-div-con";
rockchip,bits = <8 8>;
clocks = <&xin24m>;
clock-output-names = "clk_saradc";
rockchip,div-type = <CLK_DIVIDER_PLUS_ONE>;
#clock-cells = <0>;
};
};
clk_sel_con25: sel-con@00c4 {
compatible = "rockchip,rk3188-selcon";
reg = <0x00c4 0x4>;
#address-cells = <1>;
#size-cells = <1>;
clk_spi0_div: clk_spi0_div {
compatible = "rockchip,rk3188-div-con";
rockchip,bits = <0 7>;
clocks = <&clk_spi0>;
clock-output-names = "clk_spi0";
rockchip,div-type = <CLK_DIVIDER_PLUS_ONE>;
#clock-cells = <0>;
rockchip,clkops-idx =
<CLKOPS_RATE_MUX_DIV>;
};
clk_spi0: clk_spi0_mux {
compatible = "rockchip,rk3188-mux-con";
rockchip,bits = <7 1>;
clocks = <&dummy_cpll>, <&clk_gpll>;
clock-output-names = "clk_spi0";
#clock-cells = <0>;
};
clk_spi1_div: clk_spi1_div {
compatible = "rockchip,rk3188-div-con";
rockchip,bits = <8 7>;
clocks = <&clk_spi1>;
clock-output-names = "clk_spi1";
rockchip,div-type = <CLK_DIVIDER_PLUS_ONE>;
#clock-cells = <0>;
rockchip,clkops-idx =
<CLKOPS_RATE_MUX_DIV>;
};
clk_spi1: clk_spi1_mux {
compatible = "rockchip,rk3188-mux-con";
rockchip,bits = <15 1>;
clocks = <&dummy_cpll>, <&clk_gpll>;
clock-output-names = "clk_spi1";
#clock-cells = <0>;
};
};
clk_sel_con26: sel-con@00c8 {
compatible = "rockchip,rk3188-selcon";
reg = <0x00c8 0x4>;
#address-cells = <1>;
#size-cells = <1>;
ddr_div: ddr_div {
compatible = "rockchip,rk3188-div-con";
rockchip,bits = <0 2>;
clocks = <&clk_ddr>;
clock-output-names = "clk_ddr";
rockchip,div-type = <CLK_DIVIDER_USER_DEFINE>;
rockchip,div-relations =
<0x0 1
0x1 2
0x3 4>;
#clock-cells = <0>;
rockchip,flags = <(CLK_GET_RATE_NOCACHE |
CLK_SET_RATE_NO_REPARENT)>;
rockchip,clkops-idx = <CLKOPS_RATE_DDR>;
};
clk_ddr: ddr_clk_pll_mux {
compatible = "rockchip,rk3188-mux-con";
rockchip,bits = <2 1>;
clocks = <&clk_dpll>, <&clk_gpll>;
clock-output-names = "clk_ddr";
#clock-cells = <0>;
};
/* reg[5:3]: reserved */
clk_crypto: crypto_div {
compatible = "rockchip,rk3188-div-con";
rockchip,bits = <6 2>;
clocks = <&aclk_bus>;
clock-output-names = "clk_crypto";
rockchip,div-type = <CLK_DIVIDER_PLUS_ONE>;
#clock-cells = <0>;
#clock-init-cells = <1>;
};
clk_cif_pll: clk_cif_pll_mux {
compatible = "rockchip,rk3188-mux-con";
rockchip,bits = <8 1>;
clocks = <&dummy_cpll>, <&clk_gpll>;
clock-output-names = "clk_cif_pll";
#clock-cells = <0>;
};
clk_cif_out_div: clk_cif_out_div {
compatible = "rockchip,rk3188-div-con";
rockchip,bits = <9 5>;
clocks = <&clk_cif_out>;
clock-output-names = "clk_cif_out";
rockchip,div-type = <CLK_DIVIDER_PLUS_ONE>;
#clock-cells = <0>;
rockchip,clkops-idx =
<CLKOPS_RATE_MUX_DIV>;
};
/* reg[14]: reserved */
clk_cif_out: clk_cif_out_mux {
compatible = "rockchip,rk3188-mux-con";
rockchip,bits = <15 1>;
clocks = <&clk_cif_pll>, <&xin24m>;
clock-output-names = "clk_cif_out";
#clock-cells = <0>;
};
};
clk_sel_con27: sel-con@00cc {
compatible = "rockchip,rk3188-selcon";
reg = <0x00cc 0x4>;
#address-cells = <1>;
#size-cells = <1>;
dclk_lcdc0: dclk_lcdc0_mux {
compatible = "rockchip,rk3188-mux-con";
rockchip,bits = <0 2>;
clocks = <&clk_cpll>, <&clk_gpll>, <&clk_npll>;
clock-output-names = "dclk_lcdc0";
#clock-cells = <0>;
};
/* reg[7:2]: reserved */
dclk_lcdc0_div: dclk_lcdc0_div {
compatible = "rockchip,rk3188-div-con";
rockchip,bits = <8 8>;
clocks = <&dclk_lcdc0>;
clock-output-names = "dclk_lcdc0";
rockchip,div-type = <CLK_DIVIDER_PLUS_ONE>;
#clock-cells = <0>;
rockchip,clkops-idx =
<CLKOPS_RATE_RK3288_DCLK_LCDC0>;
rockchip,flags = <CLK_SET_RATE_PARENT>;
};
};
clk_sel_con28: sel-con@00d0 {
compatible = "rockchip,rk3188-selcon";
reg = <0x00d0 0x4>;
#address-cells = <1>;
#size-cells = <1>;
clk_edp_div: clk_edp_div {
compatible = "rockchip,rk3188-div-con";
rockchip,bits = <0 6>;
clocks = <&clk_edp>;
clock-output-names = "clk_edp";
rockchip,div-type = <CLK_DIVIDER_PLUS_ONE>;
#clock-cells = <0>;
rockchip,clkops-idx =
<CLKOPS_RATE_MUX_DIV>;
};
clk_edp: clk_edp_mux {
compatible = "rockchip,rk3188-mux-con";
rockchip,bits = <6 2>;
clocks = <&dummy_cpll>, <&clk_gpll>, <&clk_npll>;
clock-output-names = "clk_edp";
#clock-cells = <0>;
#clock-init-cells = <1>;
};
hclk_vio: hclk_vio_div {
compatible = "rockchip,rk3188-div-con";
rockchip,bits = <8 5>;
clocks = <&clk_gates15 11>;
clock-output-names = "hclk_vio";
rockchip,div-type = <CLK_DIVIDER_PLUS_ONE>;
#clock-cells = <0>;
#clock-init-cells = <1>;
};
/* reg[14:13]: reserved */
clk_edp_24m: edp_24m_mux {
compatible = "rockchip,rk3188-mux-con";
rockchip,bits = <15 1>;
clocks = <&edp_24m_clkin>, <&xin24m>;
clock-output-names = "clk_edp_24m";
#clock-cells = <0>;
};
};
clk_sel_con29: sel-con@00d4 {
compatible = "rockchip,rk3188-selcon";
reg = <0x00d4 0x4>;
#address-cells = <1>;
#size-cells = <1>;
ehci1phy_480m: ehci1phy_480m_mux {
compatible = "rockchip,rk3188-mux-con";
rockchip,bits = <0 2>;
clocks = <&dummy_cpll>, <&clk_gpll>, <&usbphy_480m>;
clock-output-names = "ehci1phy_480m";
#clock-cells = <0>;
};
ehci1phy_12m: ehci1phy_12m_mux {
compatible = "rockchip,rk3188-mux-con";
rockchip,bits = <2 1>;
clocks = <&clk_gates13 9>, <&ehci1phy_12m_div>;
clock-output-names = "ehci1phy_12m";
#clock-cells = <0>;
};
clkin_isp: clkin_isp {
compatible = "rockchip,rk3188-mux-con";
rockchip,bits = <3 1>;
clocks = <&clk_gates16 3>, <&pclkin_isp_inv>;
clock-output-names = "clkin_isp";
#clock-cells = <0>;
};
clkin_cif: clkin_cif {
compatible = "rockchip,rk3188-mux-con";
rockchip,bits = <4 1>;
clocks = <&clk_gates16 0>, <&pclkin_cif_inv>;
clock-output-names = "clkin_cif";
#clock-cells = <0>;
};
/* reg[5]: reserved */
dclk_lcdc1: dclk_lcdc1_mux {
compatible = "rockchip,rk3188-mux-con";
rockchip,bits = <6 2>;
clocks = <&clk_cpll>, <&clk_gpll>, <&clk_npll>;
clock-output-names = "dclk_lcdc1";
#clock-cells = <0>;
};
dclk_lcdc1_div: dclk_lcdc1_div {
compatible = "rockchip,rk3188-div-con";
rockchip,bits = <8 8>;
clocks = <&dclk_lcdc1>;
clock-output-names = "dclk_lcdc1";
rockchip,div-type = <CLK_DIVIDER_PLUS_ONE>;
#clock-cells = <0>;
rockchip,clkops-idx =
<CLKOPS_RATE_RK3288_DCLK_LCDC1>;
rockchip,flags = <CLK_SET_RATE_PARENT>;
};
};
clk_sel_con30: sel-con@00d8 {
compatible = "rockchip,rk3188-selcon";
reg = <0x00d8 0x4>;
#address-cells = <1>;
#size-cells = <1>;
aclk_rga_div: aclk_rga_div {
compatible = "rockchip,rk3188-div-con";
rockchip,bits = <0 5>;
clocks = <&aclk_rga>;
clock-output-names = "aclk_rga";
rockchip,div-type = <CLK_DIVIDER_PLUS_ONE>;
#clock-cells = <0>;
rockchip,clkops-idx =
<CLKOPS_RATE_MUX_DIV>;
};
/* reg[5]: reserved */
aclk_rga: aclk_rga_mux {
compatible = "rockchip,rk3188-mux-con";
rockchip,bits = <6 2>;
clocks = <&dummy_cpll>, <&clk_gpll>, <&usbphy_480m>;
clock-output-names = "aclk_rga";
#clock-cells = <0>;
#clock-init-cells = <1>;
};
clk_rga_div: clk_rga_div {
compatible = "rockchip,rk3188-div-con";
rockchip,bits = <8 5>;
clocks = <&clk_rga>;
clock-output-names = "clk_rga";
rockchip,div-type = <CLK_DIVIDER_PLUS_ONE>;
#clock-cells = <0>;
rockchip,clkops-idx =
<CLKOPS_RATE_MUX_DIV>;
};
/* reg[13]: reserved */
clk_rga: clk_rga_mux {
compatible = "rockchip,rk3188-mux-con";
rockchip,bits = <14 2>;
clocks = <&dummy_cpll>, <&clk_gpll>, <&usbphy_480m>;
clock-output-names = "clk_rga";
#clock-cells = <0>;
#clock-init-cells = <1>;
};
};
clk_sel_con31: sel-con@00dc {
compatible = "rockchip,rk3188-selcon";
reg = <0x00dc 0x4>;
#address-cells = <1>;
#size-cells = <1>;
aclk_vio0_div: aclk_vio0_div {
compatible = "rockchip,rk3188-div-con";
rockchip,bits = <0 5>;
clocks = <&aclk_vio0>;
clock-output-names = "aclk_vio0";
rockchip,div-type = <CLK_DIVIDER_PLUS_ONE>;
#clock-cells = <0>;
rockchip,clkops-idx =
<CLKOPS_RATE_MUX_DIV>;
rockchip,flags = <CLK_SET_RATE_NO_REPARENT>;
};
/* reg[5]: reserved */
aclk_vio0: aclk_vio0_mux {
compatible = "rockchip,rk3188-mux-con";
rockchip,bits = <6 2>;
clocks = <&clk_cpll>, <&clk_gpll>, <&usbphy_480m>;
clock-output-names = "aclk_vio0";
#clock-cells = <0>;
#clock-init-cells = <1>;
};
aclk_vio1_div: aclk_vio1_div {
compatible = "rockchip,rk3188-div-con";
rockchip,bits = <8 5>;
clocks = <&aclk_vio1>;
clock-output-names = "aclk_vio1";
rockchip,div-type = <CLK_DIVIDER_PLUS_ONE>;
#clock-cells = <0>;
rockchip,clkops-idx =
<CLKOPS_RATE_MUX_DIV>;
rockchip,flags = <CLK_SET_RATE_NO_REPARENT>;
};
/* reg[13]: reserved */
aclk_vio1: aclk_vio1_mux {
compatible = "rockchip,rk3188-mux-con";
rockchip,bits = <14 2>;
clocks = <&clk_cpll>, <&clk_gpll>, <&usbphy_480m>;
clock-output-names = "aclk_vio1";
#clock-cells = <0>;
#clock-init-cells = <1>;
};
};
clk_sel_con32: sel-con@00e0 {
compatible = "rockchip,rk3188-selcon";
reg = <0x00e0 0x4>;
#address-cells = <1>;
#size-cells = <1>;
clk_vepu_div: clk_vepu_div {
compatible = "rockchip,rk3188-div-con";
rockchip,bits = <0 5>;
clocks = <&clk_vepu>;
clock-output-names = "clk_vepu";
rockchip,div-type = <CLK_DIVIDER_PLUS_ONE>;
#clock-cells = <0>;
rockchip,clkops-idx =
<CLKOPS_RATE_MUX_DIV>;
};
/* reg[5]: reserved */
clk_vepu: clk_vepu_mux {
compatible = "rockchip,rk3188-mux-con";
rockchip,bits = <6 2>;
clocks = <&dummy_cpll>, <&clk_gpll>, <&usbphy_480m>;
clock-output-names = "clk_vepu";
#clock-cells = <0>;
#clock-init-cells = <1>;
};
clk_vdpu_div: clk_vdpu_div {
compatible = "rockchip,rk3188-div-con";
rockchip,bits = <8 5>;
clocks = <&clk_vdpu>;
clock-output-names = "clk_vdpu";
rockchip,div-type = <CLK_DIVIDER_PLUS_ONE>;
#clock-cells = <0>;
rockchip,clkops-idx =
<CLKOPS_RATE_MUX_DIV>;
};
/* reg[13]: reserved */
clk_vdpu: clk_vdpu_mux {
compatible = "rockchip,rk3188-mux-con";
rockchip,bits = <14 2>;
clocks = <&dummy_cpll>, <&clk_gpll>, <&usbphy_480m>;
clock-output-names = "clk_vdpu";
#clock-cells = <0>;
#clock-init-cells = <1>;
};
};
clk_sel_con33: sel-con@00e4 {
compatible = "rockchip,rk3188-selcon";
reg = <0x00e4 0x4>;
#address-cells = <1>;
#size-cells = <1>;
pclk_pd_pmu: pclk_pd_pmu_div {
compatible = "rockchip,rk3188-div-con";
rockchip,bits = <0 5>;
clocks = <&clk_gpll>;
clock-output-names = "pclk_pd_pmu";
rockchip,div-type = <CLK_DIVIDER_PLUS_ONE>;
#clock-cells = <0>;
#clock-init-cells = <1>;
};
/* reg[7:5]: reserved */
pclk_pd_alive: pclk_pd_alive {
compatible = "rockchip,rk3188-div-con";
rockchip,bits = <8 5>;
clocks = <&clk_gpll>;
clock-output-names = "pclk_pd_alive";
rockchip,div-type = <CLK_DIVIDER_PLUS_ONE>;
#clock-cells = <0>;
#clock-init-cells = <1>;
};
/* reg[15:13]: reserved */
};
clk_sel_con34: sel-con@00e8 {
compatible = "rockchip,rk3188-selcon";
reg = <0x00e8 0x4>;
#address-cells = <1>;
#size-cells = <1>;
clk_gpu_div: clk_gpu_div {
compatible = "rockchip,rk3188-div-con";
rockchip,bits = <0 5>;
clocks = <&clk_gpu>;
clock-output-names = "clk_gpu";
rockchip,div-type = <CLK_DIVIDER_PLUS_ONE>;
#clock-cells = <0>;
rockchip,clkops-idx =
<CLKOPS_RATE_MUX_DIV>;
rockchip,flags = <CLK_SET_RATE_PARENT_IN_ORDER>;
};
/* reg[5]: reserved */
clk_gpu: clk_gpu_mux {
compatible = "rockchip,rk3188-mux-con";
rockchip,bits = <6 2>;
clocks = <&dummy_cpll>, <&clk_gpll>, <&usbphy_480m>, <&clk_npll>;
clock-output-names = "clk_gpu";
#clock-cells = <0>;
#clock-init-cells = <1>;
};
clk_sdio1_div: clk_sdio1_div {
compatible = "rockchip,rk3188-div-con";
rockchip,bits = <8 6>;
clocks = <&clk_sdio1>;
clock-output-names = "clk_sdio1";
rockchip,div-type = <CLK_DIVIDER_PLUS_ONE>;
#clock-cells = <0>;
rockchip,clkops-idx =
<CLKOPS_RATE_MUX_EVENDIV>;
};
clk_sdio1: clk_sdio1_mux {
compatible = "rockchip,rk3188-mux-con";
rockchip,bits = <14 2>;
clocks = <&dummy_cpll>, <&clk_gpll>, <&xin24m>;
clock-output-names = "clk_sdio1";
#clock-cells = <0>;
};
};
clk_sel_con35: sel-con@00ec {
compatible = "rockchip,rk3188-selcon";
reg = <0x00ec 0x4>;
#address-cells = <1>;
#size-cells = <1>;
clk_tsp_div: clk_tsp_div {
compatible = "rockchip,rk3188-div-con";
rockchip,bits = <0 5>;
clocks = <&clk_tsp>;
clock-output-names = "clk_tsp";
rockchip,div-type = <CLK_DIVIDER_PLUS_ONE>;
#clock-cells = <0>;
rockchip,clkops-idx =
<CLKOPS_RATE_MUX_DIV>;
};
/* reg[5]: reserved */
clk_tsp: clk_tsp_mux {
compatible = "rockchip,rk3188-mux-con";
rockchip,bits = <6 2>;
clocks = <&dummy_cpll>, <&clk_gpll>, <&clk_npll>;
clock-output-names = "clk_tsp";
#clock-cells = <0>;
#clock-init-cells = <1>;
};
clk_tspout_div: clk_tspout_div {
compatible = "rockchip,rk3188-div-con";
rockchip,bits = <8 5>;
clocks = <&clk_tspout>;
clock-output-names = "clk_tspout";
rockchip,div-type = <CLK_DIVIDER_PLUS_ONE>;
#clock-cells = <0>;
rockchip,clkops-idx =
<CLKOPS_RATE_MUX_DIV>;
};
/* reg[13]: reserved */
clk_tspout: clk_tspout_mux {
compatible = "rockchip,rk3188-mux-con";
rockchip,bits = <14 2>;
clocks = <&dummy_cpll>, <&clk_gpll>, <&clk_npll>, <&io_27m_in>;
clock-output-names = "clk_tspout";
#clock-cells = <0>;
#clock-init-cells = <1>;
};
};
clk_sel_con36: sel-con@00f0 {
compatible = "rockchip,rk3188-selcon";
reg = <0x00f0 0x4>;
#address-cells = <1>;
#size-cells = <1>;
clk_core0: clk_core0_div {
compatible = "rockchip,rk3188-div-con";
rockchip,bits = <0 3>;
clocks = <&clk_core>;
clock-output-names = "clk_core0";
rockchip,div-type = <CLK_DIVIDER_PLUS_ONE>;
#clock-cells = <0>;
rockchip,clkops-idx = <CLKOPS_RATE_CORE_CHILD>;
};
/* reg[3]: reserved */
clk_core1: clk_core1_div {
compatible = "rockchip,rk3188-div-con";
rockchip,bits = <4 3>;
clocks = <&clk_core>;
clock-output-names = "clk_core1";
rockchip,div-type = <CLK_DIVIDER_PLUS_ONE>;
#clock-cells = <0>;
rockchip,clkops-idx = <CLKOPS_RATE_CORE_CHILD>;
};
/* reg[7]: reserved */
clk_core2: clk_core2_div {
compatible = "rockchip,rk3188-div-con";
rockchip,bits = <8 3>;
clocks = <&clk_core>;
clock-output-names = "clk_core2";
rockchip,div-type = <CLK_DIVIDER_PLUS_ONE>;
#clock-cells = <0>;
rockchip,clkops-idx = <CLKOPS_RATE_CORE_CHILD>;
};
/* reg[11]: reserved */
clk_core3: clk_core3_div {
compatible = "rockchip,rk3188-div-con";
rockchip,bits = <12 3>;
clocks = <&clk_core>;
clock-output-names = "clk_core3";
rockchip,div-type = <CLK_DIVIDER_PLUS_ONE>;
#clock-cells = <0>;
rockchip,clkops-idx = <CLKOPS_RATE_CORE_CHILD>;
};
/* reg[15]: reserved */
};
clk_sel_con37: sel-con@00f4 {
compatible = "rockchip,rk3188-selcon";
reg = <0x00f4 0x4>;
#address-cells = <1>;
#size-cells = <1>;
clk_l2ram: clk_l2ram_div {
compatible = "rockchip,rk3188-div-con";
rockchip,bits = <0 3>;
clocks = <&clk_core>;
clock-output-names = "clk_l2ram";
rockchip,div-type = <CLK_DIVIDER_PLUS_ONE>;
#clock-cells = <0>;
rockchip,clkops-idx = <CLKOPS_RATE_CORE_CHILD>;
};
/* reg[3]: reserved */
atclk_core: atclk_core_div {
compatible = "rockchip,rk3188-div-con";
rockchip,bits = <4 5>;
clocks = <&clk_core>;
clock-output-names = "atclk_core";
rockchip,div-type = <CLK_DIVIDER_PLUS_ONE>;
#clock-cells = <0>;
rockchip,clkops-idx = <CLKOPS_RATE_CORE_CHILD>;
};
pclk_dbg_src: pclk_core_dbg_div {
compatible = "rockchip,rk3188-div-con";
rockchip,bits = <9 5>;
clocks = <&clk_core>;
clock-output-names = "pclk_dbg_src";
rockchip,div-type = <CLK_DIVIDER_PLUS_ONE>;
#clock-cells = <0>;
rockchip,clkops-idx = <CLKOPS_RATE_CORE_CHILD>;
};
/* reg[15:14]: reserved */
};
clk_sel_con38: sel-con@00f8 {
compatible = "rockchip,rk3188-selcon";
reg = <0x00f8 0x4>;
#address-cells = <1>;
#size-cells = <1>;
clk_nandc0_div: clk_nandc0_div {
compatible = "rockchip,rk3188-div-con";
rockchip,bits = <0 5>;
clocks = <&clk_nandc0>;
clock-output-names = "clk_nandc0";
rockchip,div-type = <CLK_DIVIDER_PLUS_ONE>;
#clock-cells = <0>;
rockchip,clkops-idx =
<CLKOPS_RATE_MUX_DIV>;
};
/* reg[6:5]: reserved */
clk_nandc0: clk_nandc0_mux {
compatible = "rockchip,rk3188-mux-con";
rockchip,bits = <7 1>;
clocks = <&dummy_cpll>, <&clk_gpll>;
clock-output-names = "clk_nandc0";
#clock-cells = <0>;
};
clk_nandc1_div: clk_nandc1_div {
compatible = "rockchip,rk3188-div-con";
rockchip,bits = <8 5>;
clocks = <&clk_nandc1>;
clock-output-names = "clk_nandc1";
rockchip,div-type = <CLK_DIVIDER_PLUS_ONE>;
#clock-cells = <0>;
rockchip,clkops-idx =
<CLKOPS_RATE_MUX_DIV>;
};
/* reg[14:13]: reserved */
clk_nandc1: clk_nandc1_mux {
compatible = "rockchip,rk3188-mux-con";
rockchip,bits = <15 1>;
clocks = <&dummy_cpll>, <&clk_gpll>;
clock-output-names = "clk_nandc1";
#clock-cells = <0>;
};
};
clk_sel_con39: sel-con@00fc {
compatible = "rockchip,rk3188-selcon";
reg = <0x00fc 0x4>;
#address-cells = <1>;
#size-cells = <1>;
clk_spi2_div: clk_spi2_div {
compatible = "rockchip,rk3188-div-con";
rockchip,bits = <0 7>;
clocks = <&clk_spi2>;
clock-output-names = "clk_spi2";
rockchip,div-type = <CLK_DIVIDER_PLUS_ONE>;
#clock-cells = <0>;
rockchip,clkops-idx =
<CLKOPS_RATE_MUX_DIV>;
};
clk_spi2: clk_spi2_mux {
compatible = "rockchip,rk3188-mux-con";
rockchip,bits = <7 1>;
clocks = <&dummy_cpll>, <&clk_gpll>;
clock-output-names = "clk_spi2";
#clock-cells = <0>;
};
aclk_hevc_div: aclk_hevc_div {
compatible = "rockchip,rk3188-div-con";
rockchip,bits = <8 5>;
clocks = <&aclk_hevc>;
clock-output-names = "aclk_hevc";
rockchip,div-type = <CLK_DIVIDER_PLUS_ONE>;
#clock-cells = <0>;
rockchip,clkops-idx =
<CLKOPS_RATE_MUX_DIV>;
rockchip,flags = <CLK_SET_RATE_PARENT_IN_ORDER>;
};
/* reg[13]: reserved */
aclk_hevc: aclk_hevc_mux {
compatible = "rockchip,rk3188-mux-con";
rockchip,bits = <14 2>;
clocks = <&dummy_cpll>, <&clk_gpll>, <&clk_npll>;
clock-output-names = "aclk_hevc";
#clock-cells = <0>;
#clock-init-cells = <1>;
};
};
clk_sel_con40: sel-con@0100 {
compatible = "rockchip,rk3188-selcon";
reg = <0x0100 0x4>;
#address-cells = <1>;
#size-cells = <1>;
spdif_8ch_div: spdif_8ch_div {
compatible = "rockchip,rk3188-div-con";
rockchip,bits = <0 7>;
clocks = <&clk_spdif_pll>;
clock-output-names = "spdif_8ch_div";
rockchip,div-type = <CLK_DIVIDER_PLUS_ONE>;
#clock-cells = <0>;
};
/* reg[7]: reserved */
clk_spdif_8ch: spdif_8ch_clk_mux {
compatible = "rockchip,rk3188-mux-con";
rockchip,bits = <8 2>;
clocks = <&spdif_8ch_div>, <&spdif_8ch_frac>, <&xin12m>;
clock-output-names = "clk_spdif_8ch";
#clock-cells = <0>;
rockchip,clkops-idx =
<CLKOPS_RATE_RK3288_I2S>;
rockchip,flags = <CLK_SET_RATE_PARENT>;
};
/* reg[11:10]: reserved */
hclk_hevc: hclk_hevc_div {
compatible = "rockchip,rk3188-div-con";
rockchip,bits = <12 2>;
clocks = <&aclk_hevc>;
clock-output-names = "hclk_hevc";
rockchip,div-type = <CLK_DIVIDER_PLUS_ONE>;
#clock-cells = <0>;
#clock-init-cells = <1>;
};
/* reg[15:14]: reserved */
};
clk_sel_con41: sel-con@0104 {
compatible = "rockchip,rk3188-selcon";
reg = <0x0104 0x4>;
#address-cells = <1>;
#size-cells = <1>;
spdif_8ch_frac: spdif_8ch_frac {
compatible = "rockchip,rk3188-frac-con";
clocks = <&spdif_8ch_div>;
clock-output-names = "spdif_8ch_frac";
/* numerator denominator */
rockchip,bits = <0 32>;
rockchip,clkops-idx =
<CLKOPS_RATE_FRAC>;
#clock-cells = <0>;
};
};
clk_sel_con42: sel-con@0108 {
compatible = "rockchip,rk3188-selcon";
reg = <0x0108 0x4>;
#address-cells = <1>;
#size-cells = <1>;
clk_hevc_cabac_div: clk_hevc_cabac_div {
compatible = "rockchip,rk3188-div-con";
rockchip,bits = <0 5>;
clocks = <&clk_hevc_cabac>;
clock-output-names = "clk_hevc_cabac";
rockchip,div-type = <CLK_DIVIDER_PLUS_ONE>;
#clock-cells = <0>;
rockchip,clkops-idx =
<CLKOPS_RATE_MUX_DIV>;
rockchip,flags = <CLK_SET_RATE_PARENT_IN_ORDER>;
};
/* reg[5]: reserved */
clk_hevc_cabac: clk_hevc_cabac_mux {
compatible = "rockchip,rk3188-mux-con";
rockchip,bits = <6 2>;
clocks = <&dummy_cpll>, <&clk_gpll>, <&clk_npll>;
clock-output-names = "clk_hevc_cabac";
#clock-cells = <0>;
#clock-init-cells = <1>;
};
clk_hevc_core_div: clk_hevc_core_div {
compatible = "rockchip,rk3188-div-con";
rockchip,bits = <8 5>;
clocks = <&clk_hevc_core>;
clock-output-names = "clk_hevc_core";
rockchip,div-type = <CLK_DIVIDER_PLUS_ONE>;
#clock-cells = <0>;
rockchip,clkops-idx =
<CLKOPS_RATE_MUX_DIV>;
rockchip,flags = <CLK_SET_RATE_PARENT_IN_ORDER>;
};
/* reg[13]: reserved */
clk_hevc_core: clk_hevc_core_mux {
compatible = "rockchip,rk3188-mux-con";
rockchip,bits = <14 2>;
clocks = <&dummy_cpll>, <&clk_gpll>, <&clk_npll>;
clock-output-names = "clk_hevc_core";
#clock-cells = <0>;
#clock-init-cells = <1>;
};
};
};
/* Gate control regs */
clk_gate_cons {
compatible = "rockchip,rk-gate-cons";
#address-cells = <1>;
#size-cells = <1>;
ranges ;
clk_gates0: gate-clk@0160 {
compatible = "rockchip,rk3188-gate-clk";
reg = <0x0160 0x4>;
clocks =
<&dummy>, <&clk_apll>,
<&clk_gpll>, <&aclk_bus>,
<&hclk_bus>, <&pclk_bus>,
<&dummy>, <&aclk_bus>,
<&clk_dpll>, <&clk_gpll>,
<&clk_gpll>, <&clk_cpll>,
<&xin24m>, <&dummy>,
<&dummy>, <&dummy>;
clock-output-names =
"reserved", "reserved", /* do not use bit1 = "core_apll" */
"clk_arm_gpll", "g_aclk_bus",
"hclk_bus", "pclk_bus",
"reserved", "aclk_bus_2pmu",
"reserved", "reserved", /*"clk_ddr_dpll", "clk_ddr_gpll",*/
"reserved", "reserved", /*"clk_bus_gpll", "clk_bus_cpll",*/
"clk_acc_efuse", "reserved",
"reserved", "reserved";
rockchip,suspend-clkgating-setting=<0x0fff 0x0fff>;
#clock-cells = <1>;
};
clk_gates1: gate-clk@0164 {
compatible = "rockchip,rk3188-gate-clk";
reg = <0x0164 0x4>;
clocks =
<&xin24m>, <&xin24m>,
<&xin24m>, <&xin24m>,
<&xin24m>, <&xin24m>,
<&dummy>, <&dummy>,
<&clk_uart0_pll>, <&uart0_frac>,
<&clk_uart1_div>, <&uart1_frac>,
<&clk_uart2_div>, <&uart2_frac>,
<&clk_uart3_div>, <&uart3_frac>;
clock-output-names =
"clk_timer0", "clk_timer1",
"clk_timer2", "clk_timer3",
"clk_timer4", "clk_timer5",
"reserved", "reserved",
"clk_uart0_pll", "uart0_frac",
"clk_uart1_div", "uart1_frac",
"clk_uart2_div", "uart2_frac",
"clk_uart3_div", "uart3_frac";
rockchip,suspend-clkgating-setting=<0x0 0x0>;
#clock-cells = <1>;
};
clk_gates2: gate-clk@0168 {
compatible = "rockchip,rk3188-gate-clk";
reg = <0x0168 0x4>;
clocks =
<&aclk_peri>, <&aclk_peri>,
<&hclk_peri>, <&pclk_peri>,
<&dummy>, <&clk_mac_pll>,
<&clk_hsadc_pll>, <&clk_tsadc>,
<&clk_saradc>, <&clk_spi0>,
<&clk_spi1>, <&clk_spi2>,
<&clk_uart4_div>, <&uart4_frac>,
<&dummy>, <&dummy>;
clock-output-names =
"aclk_peri", "reserved", /*"g_aclk_periph",*/
"hclk_peri", "pclk_peri",
"reserved", "clk_mac_pll",
"clk_hsadc_pll", "clk_tsadc",
"clk_saradc", "clk_spi0",
"clk_spi1", "clk_spi2",
"clk_uart4_div", "uart4_frac",
"reserved", "reserved";
rockchip,suspend-clkgating-setting=<0x000f 0x000f>;
#clock-cells = <1>;
};
clk_gates3: gate-clk@016c {
compatible = "rockchip,rk3188-gate-clk";
reg = <0x016c 0x4>;
clocks =
<&aclk_vio0>, <&dclk_lcdc0>,
<&aclk_vio1>, <&dclk_lcdc1>,
<&clk_rga>, <&aclk_rga>,
<&ehci1phy_480m>, <&clk_cif_pll>,
<&dummy>, <&clk_vepu>,
<&dummy>, <&clk_vdpu>,
<&clk_edp_24m>, <&clk_edp>,
<&clk_isp>, <&clk_isp_jpe>;
clock-output-names =
"aclk_vio0", "dclk_lcdc0",
"aclk_vio1", "dclk_lcdc1",
"clk_rga", "aclk_rga",
"ehci1phy_480m", "clk_cif_pll",
/*Not use hclk_vpu_gate tmp, fixme*/
"reserved", "clk_vepu",
"reserved", "clk_vdpu",
"clk_edp_24m", "clk_edp",
"clk_isp", "clk_isp_jpe";
rockchip,suspend-clkgating-setting=<0x0000 0x0000>;
#clock-cells = <1>;
};
clk_gates4: gate-clk@0170 {
compatible = "rockchip,rk3188-gate-clk";
reg = <0x0170 0x4>;
clocks =
<&clk_i2s_out>, <&clk_i2s_pll>,
<&i2s_frac>, <&clk_i2s>,
<&spdif_div>, <&spdif_frac>,
<&clk_spdif>, <&spdif_8ch_div>,
<&spdif_8ch_frac>, <&clk_spdif_8ch>,
<&clk_tsp>, <&clk_tspout>,
<&clk_ddr>, <&clk_ddr>,
<&jtag_clkin>, <&dummy>;
clock-output-names =
"clk_i2s_out", "clk_i2s_pll",
"i2s_frac", "clk_i2s",
"spdif_div", "spdif_frac",
"clk_spdif", "spdif_8ch_div",
"spdif_8ch_frac", "clk_spdif_8ch",
"clk_tsp", "clk_tspout",
/* Not use these ddr gates */
"reserved", "reserved", /*"g_clk_ddrphy0", "g_clk_ddrphy1",*/
"clk_jtag", "reserved"; /*"testclk_gate_en";*/
rockchip,suspend-clkgating-setting=<0xf000 0xf000>;
#clock-cells = <1>;
};
clk_gates5: gate-clk@0174 {
compatible = "rockchip,rk3188-gate-clk";
reg = <0x0174 0x4>;
clocks =
<&clk_mac>, <&clk_mac>,
<&clk_mac>, <&clk_mac>,
<&clk_crypto>, <&clk_nandc0>,
<&clk_nandc1>, <&clk_gpu>,
<&pclk_pd_pmu>, <&xin24m>,
<&xin24m>, <&xin32k>,
<&xin24m>, <&xin24m>,
<&usbphy_480m>, <&xin24m>;
clock-output-names =
"g_clk_mac_rx", "g_clk_mac_tx",
"g_clk_mac_ref", "g_mac_refout",
"clk_crypto", "clk_nandc0",
"clk_nandc1", "clk_gpu",
"pclk_pd_pmu", "g_clk_pvtm_core",
"g_clk_pvtm_gpu", "g_hdmi_cec_clk",
"g_hdmi_hdcp_clk", "g_ps2c_clk",
"usbphy_480m", "g_mipidsi_24m";
rockchip,suspend-clkgating-setting=<0x0100 0x0100>;
#clock-cells = <1>;
};
clk_gates6: gate-clk@0178 {
compatible = "rockchip,rk3188-gate-clk";
reg = <0x0178 0x4>;
clocks =
<&hclk_peri>, <&pclk_peri>,
<&aclk_peri>, <&aclk_peri>,
<&pclk_peri>, <&pclk_peri>,
<&pclk_peri>, <&pclk_peri>,
<&pclk_peri>, <&pclk_peri>,
<&dummy>, <&pclk_peri>,
<&pclk_peri>, <&pclk_peri>,
<&pclk_peri>, <&pclk_peri>;
clock-output-names =
"g_hp_matrix", "g_pp_axi_matrix",
"g_ap_axi_matrix", "g_aclk_dmac2",
"g_pclk_spi0", "g_pclk_spi1",
"g_pclk_spi2", "g_pclk_ps2c",
"g_pclk_uart0", "g_pclk_uart1",
"reserved", "g_pclk_uart3",
"g_pclk_uart4", "g_pclk_i2c1",
"g_pclk_i2c3", "g_pclk_i2c4";
rockchip,suspend-clkgating-setting=<0x0003 0x0003>;
#clock-cells = <1>;
};
clk_gates7: gate-clk@017c {
compatible = "rockchip,rk3188-gate-clk";
reg = <0x017c 0x4>;
clocks =
<&pclk_peri>, <&pclk_peri>,
<&pclk_peri>, <&pclk_peri>,
<&hclk_peri>, <&hclk_peri>,
<&hclk_peri>, <&hclk_peri>,
<&hclk_peri>, <&hclk_peri>,
<&hclk_peri>, <&aclk_peri>,
<&hclk_peri>, <&hclk_peri>,
<&hclk_peri>, <&hclk_peri>;
clock-output-names =
"g_pclk_i2c5", "g_pclk_saradc",
"g_pclk_tsadc", "g_pclk_sim",
"g_hclk_otg0", "g_pmu_hclk_otg0",
"g_hclk_host0", "g_hclk_host1",
"g_hclk_ehci1", "g_hclk_usb_peri",
"g_hp_ahb_arbi", "g_aclk_peri_niu",
"g_h_emem_peri", "g_hclk_mem_peri",
"g_hclk_nandc0", "g_hclk_nandc1";
rockchip,suspend-clkgating-setting=<0x0c00 0xc000>;
#clock-cells = <1>;
};
clk_gates8: gate-clk@0180 {
compatible = "rockchip,rk3188-gate-clk";
reg = <0x0180 0x4>;
clocks =
<&aclk_peri>, <&pclk_peri>,
<&aclk_peri>, <&hclk_peri>,
<&hclk_peri>, <&hclk_peri>,
<&hclk_peri>, <&hclk_peri>,
<&hclk_peri>, <&hsadc_0_tsp>,
<&hsadc_1_tsp>, <&io_27m_in>,
<&aclk_peri>, <&dummy>,
<&dummy>, <&dummy>;
clock-output-names =
"g_aclk_gmac", "g_pclk_gmac",
"g_hclk_gps", "g_hclk_sdmmc",
"g_hclk_sdio0", "g_hclk_sdio1",
"g_hclk_emmc", "g_hclk_hsadc",
"g_hclk_tsp", "g_hsadc_0_tsp",
"g_hsadc_1_tsp", "g_clk_27m_tsp",
"g_aclk_peri_mmu", "reserved",
"reserved", "reserved";
rockchip,suspend-clkgating-setting=<0x0000 0x0000>;
#clock-cells = <1>;
};
clk_gates9: gate-clk@0184 {
compatible = "rockchip,rk3188-gate-clk";
reg = <0x0184 0x4>;
clocks =
<&dummy>, <&dummy>,
<&dummy>, <&dummy>,
<&dummy>, <&dummy>,
<&dummy>, <&dummy>,
<&dummy>, <&dummy>,
<&dummy>, <&dummy>,
<&dummy>, <&dummy>,
<&dummy>, <&dummy>;
clock-output-names =
"reserved", "reserved", /*"aclk_video_gate_en", "hclk_video_clock_en",*/
"reserved", "reserved",
"reserved", "reserved",
"reserved", "reserved",
"reserved", "reserved",
"reserved", "reserved",
"reserved", "reserved",
"reserved", "reserved";
rockchip,suspend-clkgating-setting=<0x0 0x0>;
#clock-cells = <1>;
};
clk_gates10: gate-clk@0188 {
compatible = "rockchip,rk3188-gate-clk";
reg = <0x0188 0x4>;
clocks =
<&pclk_bus>, <&pclk_bus>,
<&pclk_bus>, <&pclk_bus>,
<&aclk_bus>, <&aclk_bus>,
<&aclk_bus>, <&aclk_bus>,
<&hclk_bus>, <&hclk_bus>,
<&hclk_bus>, <&hclk_bus>,
<&aclk_bus>, <&aclk_bus>,
<&pclk_bus>, <&pclk_bus>;
clock-output-names =
"g_pclk_pwm", "g_pclk_timer",
"g_pclk_i2c0", "g_pclk_i2c2",
"g_aclk_intmem", "g_clk_intmem0",
"g_clk_intmem1", "g_clk_intmem2",
"g_hclk_i2s", "g_hclk_rom",
"g_hclk_spdif", "g_h_spdif_8ch",
"g_aclk_dmac1", "g_aclk_strc_sys",
"reserved", "reserved"; /*"g_p_ddrupctl0", "g_pclk_publ0";*/
//rockchip,suspend-clkgating-setting=<0xe2f1 0xe2f1>; // use sram mem no gating
rockchip,suspend-clkgating-setting=<0xf2f1 0xf2f1>; // pwm logic vol
#clock-cells = <1>;
};
clk_gates11: gate-clk@018c {
compatible = "rockchip,rk3188-gate-clk";
reg = <0x018c 0x4>;
clocks =
<&pclk_bus>, <&pclk_bus>,
<&pclk_bus>, <&pclk_bus>,
<&dummy>, <&dummy>,
<&aclk_bus>, <&hclk_bus>,
<&aclk_bus>, <&pclk_bus>,
<&pclk_bus>, <&pclk_bus>,
<&dummy>, <&dummy>,
<&dummy>, <&dummy>;
clock-output-names =
"reserved", "reserved", /*"g_p_ddrupctl1", "g_pclk_publ1",*/
"g_p_efuse_1024", "g_pclk_tzpc",
"reserved", "reserved", /*"g_nclk_ddrupctl0", "g_nclk_ddrupctl1"*/
"g_aclk_crypto", "g_hclk_crypto",
"g_aclk_ccp", "g_pclk_uart2",
"g_p_efuse_256", "g_pclk_rkpwm",
"reserved", "reserved",
"reserved", "reserved";
rockchip,suspend-clkgating-setting=<0x0033 0x0033>;
#clock-cells = <1>;
};
clk_gates12: gate-clk@0190 {
compatible = "rockchip,rk3188-gate-clk";
reg = <0x0190 0x4>;
clocks =
<&clk_core0>, <&clk_core1>,
<&clk_core2>, <&clk_core3>,
<&clk_l2ram>, <&aclk_core_m0>,
<&aclk_core_mp>, <&atclk_core>,
<&pclk_dbg_src>, <&pclk_dbg_src>,
<&pclk_dbg_src>, <&pclk_dbg_src>,
<&dummy>, <&dummy>,
<&dummy>, <&dummy>;
clock-output-names =
"clk_core0", "clk_core1",
"clk_core2", "clk_core3",
"clk_l2ram", "aclk_core_m0",
"aclk_core_mp", "atclk_core",
"pclk_dbg_src", "g_dbg_core_clk",
"g_cs_dbg_clk", "g_pclk_core_niu",
"reserved", "reserved",
"reserved", "reserved";
rockchip,suspend-clkgating-setting=<0x0ff1 0x0ff1>;
#clock-cells = <1>;
};
clk_gates13: gate-clk@0194 {
compatible = "rockchip,rk3188-gate-clk";
reg = <0x0194 0x4>;
clocks =
<&clk_sdmmc>, <&clk_sdio0>,
<&clk_sdio1>, <&clk_emmc>,
<&xin24m>, <&xin24m>,
<&xin24m>, <&xin32k>,
<&aclk_bus_src>, <&xin12m>,
<&xin24m>, <&xin24m>,
<&dummy>, <&aclk_hevc>,
<&clk_hevc_cabac>, <&clk_hevc_core>;
clock-output-names =
"clk_sdmmc", "clk_sdio0",
"clk_sdio1", "clk_emmc",
"clk_otgphy0", "clk_otgphy1",
"clk_otgphy2", "clk_otg_adp",
"g_clk_c2c_host", "g_clk_ehci1_12m",
"g_clk_lcdc_pwm0", "g_clk_lcdc_pwm1",
"g_clk_wifi", "aclk_hevc",
"clk_hevc_cabac", "clk_hevc_core";
rockchip,suspend-clkgating-setting=<0x0 0x0>;
#clock-cells = <1>;
};
clk_gates14: gate-clk@0198 {
compatible = "rockchip,rk3188-gate-clk";
reg = <0x0198 0x4>;
clocks =
<&dummy>, <&pclk_pd_alive>,
<&pclk_pd_alive>, <&pclk_pd_alive>,
<&pclk_pd_alive>, <&pclk_pd_alive>,
<&pclk_pd_alive>, <&pclk_pd_alive>,
<&pclk_pd_alive>, <&dummy>,
<&dummy>, <&pclk_pd_alive>,
<&pclk_pd_alive>, <&dummy>,
<&dummy>, <&dummy>;
clock-output-names =
"reserved", "g_pclk_gpio1",
"g_pclk_gpio2", "g_pclk_gpio3",
"g_pclk_gpio4", "g_pclk_gpio5",
"g_pclk_gpio6", "g_pclk_gpio7",
"g_pclk_gpio8", "reserved",
"reserved", "g_pclk_grf",
"g_p_alive_niu", "reserved",
"reserved", "reserved";
//rockchip,suspend-clkgating-setting=<0xffff 0xffff>;
rockchip,suspend-clkgating-setting=<0x19fe 0x19fe>;
#clock-cells = <1>;
};
clk_gates15: gate-clk@019c {
compatible = "rockchip,rk3188-gate-clk";
reg = <0x019c 0x4>;
clocks =
<&aclk_rga>, <&hclk_vio>,
<&clk_gates15 11>, <&hclk_vio>,
<&dummy>, <&clk_gates15 11>,
<&hclk_vio>, <&clk_gates15 12>,
<&hclk_vio>, <&dummy>,
<&dummy>, <&aclk_vio0>,
<&aclk_vio1>, <&aclk_rga>,
<&clk_gates15 11>, <&hclk_vio>;
clock-output-names =
"reserved", /*"g_aclk_rga"*/ "g_hclk_rga",
"g_aclk_iep", "g_hclk_iep",
"g_aclk_lcdc_iep", "g_aclk_lcdc0",
"g_hclk_lcdc0", "g_aclk_lcdc1",
"g_hclk_lcdc1", "reserved", /* "g_h_vio_ahb" */
"reserved",/*"g_hclk_vio_niu"*/ "g_aclk_vio0_niu",
"g_aclk_vio1_niu", "reserved",/*"g_aclk_rga_niu"*/
"g_aclk_vip", "g_hclk_vip";
rockchip,suspend-clkgating-setting=<0x0 0x0>;
#clock-cells = <1>;
};
clk_gates16: gate-clk@01a0 {
compatible = "rockchip,rk3188-gate-clk";
reg = <0x01a0 0x4>;
clocks =
<&pclkin_cif>, <&hclk_vio>,
<&clk_gates15 12>, <&pclkin_isp>,
<&hclk_vio>, <&hclk_vio>,
<&hclk_vio>, <&hclk_vio>,
<&hclk_vio>, <&hclk_vio>,
<&dummy>, <&dummy>,
<&dummy>, <&dummy>,
<&dummy>, <&dummy>;
clock-output-names =
"g_pclkin_cif", "g_hclk_isp",
"g_aclk_isp", "g_pclkin_isp",
"g_p_mipi_dsi0", "g_p_mipi_dsi1",
"g_p_mipi_csi", "g_pclk_lvds_phy",
"g_pclk_edp_ctrl", "g_p_hdmi_ctrl",
"reserved", "reserved", /* bit10:"g_hclk_vio2_h2p" bit11: "g_pclk_vio2_h2p" */
"reserved", "reserved",
"reserved", "reserved";
rockchip,suspend-clkgating-setting=<0x0 0x0>;
#clock-cells = <1>;
};
clk_gates17: gate-clk@01a4 {
compatible = "rockchip,rk3188-gate-clk";
reg = <0x01a4 0x4>;
clocks =
<&pclk_pd_pmu>, <&pclk_pd_pmu>,
<&pclk_pd_pmu>, <&pclk_pd_pmu>,
<&pclk_pd_pmu>, <&dummy>,
<&dummy>, <&dummy>,
<&dummy>, <&dummy>,
<&dummy>, <&dummy>,
<&dummy>, <&dummy>,
<&dummy>, <&dummy>;
clock-output-names =
"g_pclk_pmu", "g_pclk_intmem1",
"g_pclk_pmu_niu", "g_pclk_sgrf",
"g_pclk_gpio0", "reserved",
"reserved", "reserved",
"reserved", "reserved",
"reserved", "reserved",
"reserved", "reserved",
"reserved", "reserved";
rockchip,suspend-clkgating-setting=<0x01f 0x01f>;
#clock-cells = <1>;
};
clk_gates18: gate-clk@01a8 {
compatible = "rockchip,rk3188-gate-clk";
reg = <0x01a8 0x4>;
clocks =
<&clk_gpu>, <&dummy>,
<&dummy>, <&dummy>,
<&dummy>, <&dummy>,
<&dummy>, <&dummy>,
<&dummy>, <&dummy>,
<&dummy>, <&dummy>,
<&dummy>, <&dummy>,
<&dummy>, <&dummy>;
clock-output-names =
"reserved", /*"g_aclk_gpu",*/ "reserved",
"reserved", "reserved",
"reserved", "reserved",
"reserved", "reserved",
"reserved", "reserved",
"reserved", "reserved",
"reserved", "reserved",
"reserved", "reserved";
rockchip,suspend-clkgating-setting=<0x0 0x0>;
#clock-cells = <1>;
};
};
};
};
};