关键词：rk3366.dtsi , linux-4.4, rockchip, dts
dts — rk3366.dtsi
/*
* Copyright (c) 2016 Fuzhou Rockchip Electronics Co., Ltd
*
* This file is dual-licensed: you can use it either under the terms
* of the GPL or the X11 license, at your option. Note that this dual
* licensing only applies to this file, and not this project as a
* whole.
*
* a) This library is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
* published by the Free Software Foundation; either version 2 of the
* License, or (at your option) any later version.
*
* This library is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* Or, alternatively,
*
* b) Permission is hereby granted, free of charge, to any person
* obtaining a copy of this software and associated documentation
* files (the "Software"), to deal in the Software without
* restriction, including without limitation the rights to use,
* copy, modify, merge, publish, distribute, sublicense, and/or
* sell copies of the Software, and to permit persons to whom the
* Software is furnished to do so, subject to the following
* conditions:
*
* The above copyright notice and this permission notice shall be
* included in all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
* EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
* OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
* NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
* HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
* OTHER DEALINGS IN THE SOFTWARE.
*/
#include <dt-bindings/clock/rk3366-cru.h>
#include <dt-bindings/gpio/gpio.h>
#include <dt-bindings/interrupt-controller/irq.h>
#include <dt-bindings/interrupt-controller/arm-gic.h>
#include <dt-bindings/pinctrl/rockchip.h>
#include <dt-bindings/display/mipi_dsi.h>
#include <dt-bindings/power/rk3366-power.h>
#include <dt-bindings/soc/rockchip,boot-mode.h>
#include <dt-bindings/thermal/thermal.h>
#include <dt-bindings/display/drm_mipi_dsi.h>
#include <dt-bindings/display/media-bus-format.h>
/ {
compatible = "rockchip,rk3366";
interrupt-parent = <&gic>;
#address-cells = <2>;
#size-cells = <2>;
aliases {
i2c0 = &i2c0;
i2c1 = &i2c1;
i2c2 = &i2c2;
i2c3 = &i2c3;
i2c4 = &i2c4;
i2c5 = &i2c5;
serial0 = &uart0;
serial2 = &uart2;
serial3 = &uart3;
spi0 = &spi0;
spi1 = &spi1;
};
cpus {
#address-cells = <0x2>;
#size-cells = <0x0>;
cpu0: cpu@0 {
device_type = "cpu";
compatible = "arm,cortex-a53","arm,armv8";
reg = <0x0 0x0>;
enable-method = "psci";
clocks = <&cru ARMCLK>;
operating-points-v2 = <&cpu0_opp_table>;
cpu-idle-states = <&CPU_SLEEP &CLUSTER_SLEEP>;
#cooling-cells = <2>; /* min followed by max */
dynamic-power-coefficient = <166>;
};
cpu1: cpu@1 {
device_type = "cpu";
compatible = "arm,cortex-a53","arm,armv8";
reg = <0x0 0x1>;
enable-method = "psci";
operating-points-v2 = <&cpu0_opp_table>;
cpu-idle-states = <&CPU_SLEEP &CLUSTER_SLEEP>;
};
cpu2: cpu@2 {
device_type = "cpu";
compatible = "arm,cortex-a53","arm,armv8";
reg = <0x0 0x2>;
enable-method = "psci";
operating-points-v2 = <&cpu0_opp_table>;
cpu-idle-states = <&CPU_SLEEP &CLUSTER_SLEEP>;
};
cpu3: cpu@3 {
device_type = "cpu";
compatible = "arm,cortex-a53","arm,armv8";
reg = <0x0 0x3>;
enable-method = "psci";
operating-points-v2 = <&cpu0_opp_table>;
cpu-idle-states = <&CPU_SLEEP &CLUSTER_SLEEP>;
};
idle-states {
entry-method = "psci";
CPU_SLEEP: cpu-sleep {
compatible = "arm,idle-state";
local-timer-stop;
arm,psci-suspend-param = <0x0010000>;
entry-latency-us = <120>;
exit-latency-us = <250>;
min-residency-us = <900>;
};
CLUSTER_SLEEP: cluster-sleep {
compatible = "arm,idle-state";
local-timer-stop;
arm,psci-suspend-param = <0x1010000>;
entry-latency-us = <400>;
exit-latency-us = <500>;
min-residency-us = <2000>;
};
};
};
cpu0_opp_table: opp_table0 {
compatible = "operating-points-v2";
opp-shared;
nvmem-cells = <&cpu_leakage>;
nvmem-cell-names = "cpu_leakage";
opp-408000000 {
opp-hz = /bits/ 64 <408000000>;
opp-microvolt = <950000 950000 1250000>;
clock-latency-ns = <40000>;
opp-suspend;
};
opp-600000000 {
opp-hz = /bits/ 64 <600000000>;
opp-microvolt = <950000 950000 1250000>;
};
opp-816000000 {
opp-hz = /bits/ 64 <816000000>;
opp-microvolt = <1000000 1000000 1250000>;
};
opp-1008000000 {
opp-hz = /bits/ 64 <1008000000>;
opp-microvolt = <1075000 1075000 1250000>;
};
opp-1200000000 {
opp-hz = /bits/ 64 <1200000000>;
opp-microvolt = <1175000 1175000 1250000>;
};
opp-1296000000 {
opp-hz = /bits/ 64 <1296000000>;
opp-microvolt = <1250000 1250000 1250000>;
};
};
psci {
compatible = "arm,psci-1.0";
method = "smc";
};
timer {
compatible = "arm,armv8-timer";
interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>,
<GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>,
<GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>,
<GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>;
};
arm-pmu {
compatible = "arm,cortex-a53-pmu";
interrupts = <GIC_SPI 112 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 115 IRQ_TYPE_LEVEL_HIGH>;
interrupt-affinity = <&cpu0>,
<&cpu1>,
<&cpu2>,
<&cpu3>;
};
xin24m: xin24m {
compatible = "fixed-clock";
#clock-cells = <0>;
clock-frequency = <24000000>;
clock-output-names = "xin24m";
};
gic: interrupt-controller@ffb71000 {
compatible = "arm,gic-400";
interrupt-controller;
#interrupt-cells = <3>;
#address-cells = <0>;
reg = <0x0 0xffb71000 0x0 0x1000>,
<0x0 0xffb72000 0x0 0x1000>,
<0x0 0xffb74000 0x0 0x2000>,
<0x0 0xffb76000 0x0 0x2000>;
interrupts = <GIC_PPI 9
(GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>;
};
nandc0: nandc@ff0c0000 {
compatible = "rockchip,rk-nandc";
reg = <0x0 0xff0c0000 0x0 0x4000>;
interrupts = <GIC_SPI 38 IRQ_TYPE_LEVEL_HIGH>;
nandc_id = <0>;
clocks = <&cru SCLK_NANDC0>, <&cru HCLK_NANDC0>;
clock-names = "clk_nandc", "hclk_nandc";
status = "disabled";
};
saradc: saradc@ff100000 {
compatible = "rockchip,saradc";
reg = <0x0 0xff100000 0x0 0x100>;
interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>;
#io-channel-cells = <1>;
clocks = <&cru SCLK_SARADC>, <&cru PCLK_SARADC>;
clock-names = "saradc", "apb_pclk";
status = "disabled";
};
spi0: spi@ff110000 {
compatible = "rockchip,rk3368-spi", "rockchip,rk3066-spi";
reg = <0x0 0xff110000 0x0 0x1000>;
clocks = <&cru SCLK_SPI0>, <&cru PCLK_SPI0>;
clock-names = "spiclk", "apb_pclk";
interrupts = <GIC_SPI 44 IRQ_TYPE_LEVEL_HIGH>;
pinctrl-names = "default";
pinctrl-0 = <&spi0_clk &spi0_tx &spi0_rx &spi0_cs0>;
#address-cells = <1>;
#size-cells = <0>;
status = "disabled";
};
spi1: spi@ff120000 {
compatible = "rockchip,rk3368-spi", "rockchip,rk3066-spi";
reg = <0x0 0xff120000 0x0 0x1000>;
clocks = <&cru SCLK_SPI1>, <&cru PCLK_SPI1>;
clock-names = "spiclk", "apb_pclk";
interrupts = <GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH>;
pinctrl-names = "default";
pinctrl-0 = <&spi1_clk &spi1_tx &spi1_rx &spi1_cs0>;
#address-cells = <1>;
#size-cells = <0>;
status = "disabled";
};
scr: rkscr@ff1d0000 {
compatible = "rockchip-scr";
reg = <0x0 0xff1d0000 0x0 0x10000>;
interrupts = <GIC_SPI 43 IRQ_TYPE_LEVEL_HIGH>;
#address-cells = <1>;
#size-cells = <0>;
pinctrl-names = "default";
pinctrl-0 = <&scr_io &scr_detect &scr_rst &scr_clk>;
clocks = <&cru PCLK_SIM>;
clock-names = "g_pclk_sim_card";
status = "disabled";
};
thermal-zones {
soc_thermal: soc-thermal {
polling-delay-passive = <100>; /* milliseconds */
polling-delay = <1000>; /* milliseconds */
sustainable-power = <1600>; /* milliwatts */
thermal-sensors = <&tsadc 0>;
trips {
threshold: trip-point-0 {
temperature = <70000>; /* millicelsius */
hysteresis = <2000>; /* millicelsius */
type = "passive";
};
target: trip-point-1 {
temperature = <85000>; /* millicelsius */
hysteresis = <2000>; /* millicelsius */
type = "passive";
};
soc_crit: soc-crit {
temperature = <115000>; /* millicelsius */
hysteresis = <2000>; /* millicelsius */
type = "critical";
};
};
cooling-maps {
map0 {
trip = <&target>;
cooling-device =
<&cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
};
map1 {
trip = <&target>;
cooling-device =
<&gpu THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
};
};
};
gpu_thermal: gpu-thermal {
polling-delay-passive = <100>; /* milliseconds */
polling-delay = <1000>; /* milliseconds */
thermal-sensors = <&tsadc 1>;
};
};
tsadc: tsadc@ff260000 {
compatible = "rockchip,rk3366-tsadc";
reg = <0x0 0xff260000 0x0 0x100>;
interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&cru SCLK_TSADC>, <&cru PCLK_TSADC>;
clock-names = "tsadc", "apb_pclk";
resets = <&cru SRST_TSADC>;
reset-names = "tsadc-apb";
pinctrl-names = "default";
pinctrl-0 = <&tsadc_gpio>;
#thermal-sensor-cells = <1>;
rockchip,hw-tshut-temp = <120000>;
status = "disabled";
};
sdmmc: dwmmc@ff400000 {
compatible = "rockchip,rk3366-dw-mshc","rockchip,rk3288-dw-mshc";
clock-freq-min-max = <400000 150000000>;
clocks = <&cru HCLK_SDMMC>, <&cru SCLK_SDMMC>,
<&cru SCLK_SDMMC_DRV>, <&cru SCLK_SDMMC_SAMPLE>;
clock-names = "biu", "ciu", "ciu-drive", "ciu-sample";
fifo-depth = <0x100>;
interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>;
reg = <0x0 0xff400000 0x0 0x4000>;
status = "disabled";
};
sdio: dwmmc@ff410000 {
compatible = "rockchip,rk3366-dw-mshc","rockchip,rk3288-dw-mshc";
clock-freq-min-max = <400000 150000000>;
clocks = <&cru HCLK_SDIO>, <&cru SCLK_SDIO0>,
<&cru SCLK_SDIO0_DRV>, <&cru SCLK_SDIO0_SAMPLE>;
clock-names = "biu", "ciu", "ciu-drive", "ciu-sample";
fifo-depth = <0x100>;
interrupts = <GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>;
reg = <0x0 0xff410000 0x0 0x4000>;
status = "disabled";
};
emmc: dwmmc@ff420000 {
compatible = "rockchip,rk3366-dw-mshc","rockchip,rk3288-dw-mshc";
clock-freq-min-max = <400000 150000000>;
clocks = <&cru HCLK_EMMC>, <&cru SCLK_EMMC>,
<&cru SCLK_EMMC_DRV>, <&cru SCLK_EMMC_SAMPLE>;
clock-names = "biu", "ciu", "ciu-drive", "ciu-sample";
fifo-depth = <0x100>;
interrupts = <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>;
reg = <0x0 0xff420000 0x0 0x4000>;
status = "disabled";
};
gmac: eth@ff440000 {
compatible = "rockchip,rk3366-gmac";
reg = <0x0 0xff440000 0x0 0x10000>;
rockchip,grf = <&grf>;
interrupts = <GIC_SPI 27 IRQ_TYPE_LEVEL_HIGH>;
interrupt-names = "macirq";
clocks = <&cru SCLK_MAC>, <&cru SCLK_MAC_RX>,
<&cru SCLK_MAC_TX>, <&cru SCLK_MACREF>,
<&cru SCLK_MACREF_OUT>, <&cru ACLK_GMAC>,
<&cru PCLK_GMAC>;
clock-names = "stmmaceth", "mac_clk_rx",
"mac_clk_tx", "clk_mac_ref",
"clk_mac_refout", "aclk_mac",
"pclk_mac";
resets = <&cru SRST_MAC>;
reset-names = "stmmaceth";
status = "disabled";
};
i2c0: i2c@ff650000 {
compatible = "rockchip,rk3368-i2c", "rockchip,rk3288-i2c";
reg = <0x0 0xff728000 0x0 0x1000>;
clocks = <&cru PCLK_I2C0>;
clock-names = "i2c";
interrupts = <GIC_SPI 60 IRQ_TYPE_LEVEL_HIGH>;
pinctrl-names = "default";
pinctrl-0 = <&i2c0_xfer>;
#address-cells = <1>;
#size-cells = <0>;
status = "disabled";
};
i2c2: i2c@ff140000 {
compatible = "rockchip,rk3368-i2c", "rockchip,rk3288-i2c";
reg = <0x0 0xff140000 0x0 0x1000>;
interrupts = <GIC_SPI 62 IRQ_TYPE_LEVEL_HIGH>;
#address-cells = <1>;
#size-cells = <0>;
clock-names = "i2c";
clocks = <&cru PCLK_I2C2>;
pinctrl-names = "default";
pinctrl-0 = <&i2c2_xfer>;
status = "disabled";
};
i2c3: i2c@ff150000 {
compatible = "rockchip,rk3368-i2c", "rockchip,rk3288-i2c";
reg = <0x0 0xff150000 0x0 0x1000>;
interrupts = <GIC_SPI 63 IRQ_TYPE_LEVEL_HIGH>;
#address-cells = <1>;
#size-cells = <0>;
clock-names = "i2c";
clocks = <&cru PCLK_I2C3>;
pinctrl-names = "default";
pinctrl-0 = <&i2c3_xfer>;
status = "disabled";
};
i2c4: i2c@ff160000 {
compatible = "rockchip,rk3368-i2c", "rockchip,rk3288-i2c";
reg = <0x0 0xff160000 0x0 0x1000>;
interrupts = <GIC_SPI 64 IRQ_TYPE_LEVEL_HIGH>;
#address-cells = <1>;
#size-cells = <0>;
clock-names = "i2c";
clocks = <&cru PCLK_I2C4>;
pinctrl-names = "default";
pinctrl-0 = <&i2c4_xfer>;
status = "disabled";
};
i2c5: i2c@ff170000 {
compatible = "rockchip,rk3368-i2c", "rockchip,rk3288-i2c";
reg = <0x0 0xff170000 0x0 0x1000>;
interrupts = <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>;
#address-cells = <1>;
#size-cells = <0>;
clock-names = "i2c";
clocks = <&cru PCLK_I2C5>;
pinctrl-names = "default";
pinctrl-0 = <&i2c5_xfer>;
status = "disabled";
};
uart0: serial@ff180000 {
compatible = "rockchip,rk3368-uart", "snps,dw-apb-uart";
reg = <0x0 0xff180000 0x0 0x100>;
clock-frequency = <24000000>;
clocks = <&cru SCLK_UART0>, <&cru PCLK_UART0>;
clock-names = "baudclk", "apb_pclk";
interrupts = <GIC_SPI 55 IRQ_TYPE_LEVEL_HIGH>;
reg-shift = <2>;
reg-io-width = <4>;
pinctrl-names = "default";
pinctrl-0 = <&uart0_xfer &uart0_cts &uart0_rts>;
status = "disabled";
};
uart3: serial@ff1b0000 {
compatible = "rockchip,rk3368-uart", "snps,dw-apb-uart";
reg = <0x0 0xff1b0000 0x0 0x100>;
clock-frequency = <24000000>;
clocks = <&cru SCLK_UART3>, <&cru PCLK_UART3>;
clock-names = "baudclk", "apb_pclk";
interrupts = <GIC_SPI 58 IRQ_TYPE_LEVEL_HIGH>;
reg-shift = <2>;
reg-io-width = <4>;
pinctrl-names = "default";
pinctrl-0 = <&uart3_xfer &uart3_cts &uart3_rts>;
status = "disabled";
};
usb_host0_ehci: usb@ff480000 {
compatible = "generic-ehci";
reg = <0x0 0xff480000 0x0 0x20000>;
interrupts = <GIC_SPI 24 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&cru SCLK_USBPHY480M>, <&cru HCLK_HOST>;
clock-names = "usbphy_480m", "hclk_host0";
phys = <&u2phy_host>;
phy-names = "usb";
status = "disabled";
};
usb_host0_ohci: usb@ff4a0000 {
compatible = "generic-ohci";
reg = <0x0 0xff4a0000 0x0 0x20000>;
interrupts = <GIC_SPI 25 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&cru SCLK_USBPHY480M>, <&cru HCLK_HOST>;
clock-names = "usbphy_480m", "hclk_host0";
phys = <&u2phy_host>;
phy-names = "usb";
status = "disabled";
};
usb_otg: usb@ff4c0000 {
compatible = "rockchip,rk3368-usb", "rockchip,rk3066-usb",
"snps,dwc2";
reg = <0x0 0xff4c0000 0x0 0x40000>;
interrupts = <GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&cru HCLK_OTG>;
clock-names = "otg";
dr_mode = "otg";
g-np-tx-fifo-size = <16>;
g-rx-fifo-size = <280>;
g-tx-fifo-size = <256 128 128 64 32 16>;
g-use-dma;
status = "disabled";
};
i2c1: i2c@ff660000 {
compatible = "rockchip,rk3368-i2c", "rockchip,rk3288-i2c";
reg = <0x0 0xff660000 0x0 0x1000>;
interrupts = <GIC_SPI 61 IRQ_TYPE_LEVEL_HIGH>;
#address-cells = <1>;
#size-cells = <0>;
clock-names = "i2c";
clocks = <&cru PCLK_I2C1>;
pinctrl-names = "default";
pinctrl-0 = <&i2c1_xfer>;
status = "disabled";
};
efuse: efuse@ff670000 {
compatible = "rockchip,rk3366-efuse";
reg = <0x0 0xff670000 0x0 0x20>;
#address-cells = <1>;
#size-cells = <1>;
clocks = <&cru PCLK_EFUSE_256>;
clock-names = "pclk_efuse";
/* Data cells */
cpu_leakage: cpu-leakage {
reg = <0x17 0x1>;
};
gpu_leakage: gpu-leakage {
reg = <0x18 0x1>;
};
logic_leakage: logic-leakage {
reg = <0x19 0x1>;
};
wafer_info: wafer-info {
reg = <0x1c 0x1>;
};
};
pwm0: pwm@ff680000 {
compatible = "rockchip,rk3368-pwm", "rockchip,rk3288-pwm";
reg = <0x0 0xff680000 0x0 0x10>;
#pwm-cells = <3>;
pinctrl-names = "active";
pinctrl-0 = <&pwm0_pin>;
clocks = <&cru PCLK_RKPWM>;
clock-names = "pwm";
status = "disabled";
};
pwm1: pwm@ff680010 {
compatible = "rockchip,rk3368-pwm", "rockchip,rk3288-pwm";
reg = <0x0 0xff680010 0x0 0x10>;
#pwm-cells = <3>;
pinctrl-names = "active";
pinctrl-0 = <&pwm1_pin>;
clocks = <&cru PCLK_RKPWM>;
clock-names = "pwm";
status = "disabled";
};
pwm2: pwm@ff680020 {
compatible = "rockchip,rk3368-pwm", "rockchip,rk3288-pwm";
reg = <0x0 0xff680020 0x0 0x10>;
#pwm-cells = <3>;
clocks = <&cru PCLK_RKPWM>;
clock-names = "pwm";
status = "disabled";
};
pwm3: pwm@ff680030 {
compatible = "rockchip,rk3368-pwm", "rockchip,rk3288-pwm";
reg = <0x0 0xff680030 0x0 0x10>;
#pwm-cells = <3>;
pinctrl-names = "active";
pinctrl-0 = <&pwm3_t2_pin>;
clocks = <&cru PCLK_RKPWM>;
clock-names = "pwm";
status = "disabled";
};
uart2: serial@ff690000 {
compatible = "rockchip,rk3366-uart", "snps,dw-apb-uart";
reg = <0x0 0xff690000 0x0 0x100>;
interrupts = <GIC_SPI 57 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&cru SCLK_UART2>, <&cru PCLK_UART2>;
clock-names = "baudclk", "apb_pclk";
reg-shift = <2>;
reg-io-width = <4>;
pinctrl-names = "default";
pinctrl-0 = <&uart2_t1_xfer>;
status = "disabled";
};
pmu: power-management@ff730000 {
compatible = "rockchip,rk3366-pmu", "syscon", "simple-mfd";
reg = <0x0 0xff730000 0x0 0x1000>;
power: power-controller {
compatible = "rockchip,rk3366-power-controller";
#power-domain-cells = <1>;
#address-cells = <1>;
#size-cells = <0>;
/*
* Note: Although SCLK_* are the working clocks
* of device without including on the NOC, needed for
* synchronous reset.
*
* The clocks on the which NOC:
* ACLK_IEP/ACLK_VOP_FULL are on ACLK_VIO0_NOC.
* ACLK_RGA/ACLK_VOP_LITE are on ACLK_VIO1_NOC.
* ACLK_ISP is on ACLK_ISP_NOC.
* ACLK_HDCP is on ACLK_HDCP_NOC.
* The others (HCLK_*,PLCK_*) are on HCLK_VIO_NOC.
*
* Which clock are device clocks:
* clocks devices
* *_IEP IEP:Image Enhancement Processor
* *_ISP ISP:Image Signal Processing
* *_VOP* VOP:Visual Output Processor
* *_RGA RGA
* *_DPHY* LVDS
* *_HDMI HDMI
* *_MIPI_* MIPI/LVDS
*/
pd_vio@RK3366_PD_VIO {
reg = <RK3366_PD_VIO>;
clocks = <&cru ACLK_IEP>,
<&cru ACLK_ISP>,
<&cru ACLK_RGA>,
<&cru ACLK_HDCP>,
<&cru ACLK_VOP_FULL>,
<&cru ACLK_VOP_LITE>,
<&cru ACLK_VOP_IEP>,
<&cru DCLK_VOP_FULL>,
<&cru DCLK_VOP_LITE>,
<&cru HCLK_IEP>,
<&cru HCLK_ISP>,
<&cru HCLK_RGA>,
<&cru HCLK_VOP_FULL>,
<&cru HCLK_VOP_LITE>,
<&cru HCLK_VIO_HDCPMMU>,
<&cru PCLK_DPHYTX>,
<&cru PCLK_HDMI_CTRL>,
<&cru PCLK_HDCP>,
<&cru PCLK_MIPI_DSI0>,
<&cru SCLK_VOP_FULL_PWM>,
<&cru SCLK_HDCP>,
<&cru SCLK_ISP>,
<&cru SCLK_RGA>,
<&cru SCLK_HDMI_CEC>,
<&cru SCLK_HDMI_HDCP>;
pm_qos = <&qos_iep>, <&qos_isp_r0>,
<&qos_isp_r1>, <&qos_isp_w0>,
<&qos_isp_w1>, <&qos_vop0_w>,
<&qos_rga_r>, <&qos_rga_w>,
<&qos_vop0_r>, <&qos_vop1_r>,
<&qos_hdcp>;
};
/*
* Note: ACLK_VCODEC/HCLK_VCODEC are VPU clocks
* that on the ACLK_VCODEC_NOC and
* HCLK_VCODEC_NOC.
*/
pd_vpu@RK3366_PD_VPU {
reg = <RK3366_PD_VPU>;
clocks = <&cru ACLK_VIDEO>,
<&cru HCLK_VIDEO>;
pm_qos = <&qos_vpu_r>, <&qos_vpu_w>;
};
/*
* Note: ACLK_RKVDEC/HCLK_RKVDEC are RKVDEC
* clocks that on the ACLK_RKVDEC_NOC and
* HCLK_RKVDEC_NOC.
*/
pd_rkvdec@RK3366_PD_RKVDEC {
reg = <RK3366_PD_RKVDEC>;
clocks = <&cru ACLK_RKVDEC>,
<&cru HCLK_RKVDEC>,
<&cru SCLK_HEVC_CABAC>,
<&cru SCLK_HEVC_CORE>;
pm_qos = <&qos_rkvdec_r>, <&qos_rkvdec_w>;
};
/*
* Note: ACLK_GPU is the GPU clock
* that on the ACLK_GPU_NOC.
*/
pd_gpu@RK3366_PD_GPU {
reg = <RK3366_PD_GPU>;
clocks = <&cru ACLK_GPU>;
pm_qos = <&qos_gpu>;
};
};
};
pmugrf: syscon@ff738000 {
compatible = "rockchip,rk3366-pmugrf", "syscon", "simple-mfd";
reg = <0x0 0xff738000 0x0 0x1000>;
reboot-mode {
compatible = "syscon-reboot-mode";
offset = <0x200>;
mode-normal = <BOOT_NORMAL>;
mode-recovery = <BOOT_RECOVERY>;
mode-fastboot = <BOOT_FASTBOOT>;
mode-loader = <BOOT_BL_DOWNLOAD>;
};
pmu_pvtm: pmu-pvtm {
compatible = "rockchip,rk3366-pmu-pvtm";
clocks = <&cru SCLK_PVTM_PMU>;
clock-names = "pmu";
status = "disabled";
};
};
amba {
compatible = "arm,amba-bus";
#address-cells = <2>;
#size-cells = <2>;
ranges;
dmac_peri: dma-controller@ff250000 {
compatible = "arm,pl330", "arm,primecell";
reg = <0x0 0xff250000 0x0 0x4000>;
interrupts = <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>;
#dma-cells = <1>;
clocks = <&cru ACLK_DMAC_PERI>;
clock-names = "apb_pclk";
peripherals-req-type-burst;
};
dmac_bus: dma-controller@ff600000 {
compatible = "arm,pl330", "arm,primecell";
reg = <0x0 0xff600000 0x0 0x4000>;
interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>;
#dma-cells = <1>;
clocks = <&cru ACLK_DMAC_BUS>;
clock-names = "apb_pclk";
peripherals-req-type-burst;
};
};
cru: clock-controller@ff760000 {
compatible = "rockchip,rk3366-cru";
reg = <0x0 0xff760000 0x0 0x1000>;
rockchip,grf = <&grf>;
#clock-cells = <1>;
#reset-cells = <1>;
assigned-clocks =
<&cru SCLK_WIFIDSP>, <&cru SCLK_32K>,
<&cru DCLK_VOP_FULL>, <&cru DCLK_VOP_LITE>,
<&cru SCLK_I2S_8CH_SRC>, <&cru SCLK_I2S_2CH_SRC>,
<&cru SCLK_SPDIF_8CH_SRC>,
<&cru PLL_CPLL>, <&cru PLL_GPLL>,
<&cru PLL_NPLL>, <&cru PLL_MPLL>,
<&cru PLL_WPLL>, <&cru PLL_BPLL>,
<&cru ACLK_VOP_FULL>, <&cru ACLK_VOP_LITE>,
<&cru HCLK_VOP_LITE>,<&cru HCLK_VOP_LITE>,
<&cru ACLK_BUS>, <&cru ACLK_PERI0>,
<&cru ACLK_PERI1>;
assigned-clock-rates =
<0>, <0>,
<0>, <0>,
<0>, <0>,
<0>,
<750000000>, <576000000>,
<594000000>, <594000000>,
<960000000>, <520000000>,
<375000000>, <288000000>,
<100000000>, <100000000>,
<288000000>, <288000000>,
<144000000>;
assigned-clock-parents =
<&cru SCLK_WIFI_WPLL>, <&cru SCLK_32K_INTR>,
<&cru SCLK_MPLL_SRC>, <&cru PLL_NPLL>,
<&cru PLL_GPLL>, <&cru PLL_GPLL>,
<&cru PLL_GPLL>;
};
grf: syscon@ff770000 {
compatible = "rockchip,rk3366-grf", "syscon", "simple-mfd";
reg = <0x0 0xff770000 0x0 0x1000>;
#address-cells = <1>;
#size-cells = <1>;
u2phy: usb2-phy@700 {
compatible = "rockchip,rk3366-usb2phy";
reg = <0x700 0x2c>;
clocks = <&cru SCLK_OTG_PHY0>;
clock-names = "phyclk";
#clock-cells = <0>;
clock-output-names = "sclk_otgphy0_480m";
u2phy_host: host-port {
#phy-cells = <0>;
interrupts = <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>;
interrupt-names = "linestate";
status = "okay";
};
};
pvtm: pvtm {
compatible = "rockchip,rk3366-pvtm";
clocks = <&cru SCLK_PVTM_CORE>, <&cru SCLK_PVTM_GPU>;
clock-names = "core", "gpu";
status = "disabled";
};
};
wdt: watchdog@ff800000 {
compatible = "snps,dw-wdt";
reg = <0x0 0xff800000 0x0 0x100>;
clocks = <&cru PCLK_WDT>;
interrupts = <GIC_SPI 79 IRQ_TYPE_LEVEL_HIGH>;
status = "disabled";
};
rktimer: rktimer@ff810000 {
compatible = "rockchip,rk3288-timer";
reg = <0x0 0xff810000 0x0 0x1000>;
interrupts = <GIC_SPI 66 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&cru PCLK_TIMER0>, <&cru SCLK_TIMER0>;
clock-names = "pclk", "timer";
};
spdif: spdif@ff880000 {
compatible = "rockchip,rk3366-spdif";
reg = <0x0 0xff880000 0x0 0x1000>;
interrupts = <GIC_SPI 54 IRQ_TYPE_LEVEL_HIGH>;
dmas = <&dmac_bus 3>;
dma-names = "tx";
clock-names = "mclk", "hclk";
clocks = <&cru SCLK_SPDIF_8CH>, <&cru HCLK_SPDIF>;
pinctrl-names = "default";
pinctrl-0 = <&spdif_bus>;
status = "disabled";
};
i2s_2ch: i2s-2ch@ff890000 {
compatible = "rockchip,rk3366-i2s", "rockchip,rk3066-i2s";
reg = <0x0 0xff890000 0x0 0x1000>;
interrupts = <GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>;
dmas = <&dmac_bus 6>, <&dmac_bus 7>;
dma-names = "tx", "rx";
clock-names = "i2s_clk", "i2s_hclk";
clocks = <&cru SCLK_I2S_2CH>, <&cru HCLK_I2S_2CH>;
status = "disabled";
};
i2s_8ch: i2s-8ch@ff898000 {
compatible = "rockchip,rk3366-i2s", "rockchip,rk3066-i2s";
reg = <0x0 0xff898000 0x0 0x1000>;
interrupts = <GIC_SPI 53 IRQ_TYPE_LEVEL_HIGH>;
dmas = <&dmac_bus 0>, <&dmac_bus 1>;
dma-names = "tx", "rx";
clock-names = "i2s_clk", "i2s_hclk";
clocks = <&cru SCLK_I2S_8CH>, <&cru HCLK_I2S_8CH>;
pinctrl-names = "default";
pinctrl-0 = <&i2s_8ch_bus>;
status = "disabled";
};
display_subsystem: display-subsystem {
compatible = "rockchip,display-subsystem";
ports = <&vopb_out>, <&vopl_out>;
status = "disabled";
};
vopl: vop@ff8f0000 {
compatible = "rockchip,rk3366-vop-lit";
reg = <0x0 0xff8f0000 0x0 0x900>;
interrupts = <GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&cru ACLK_VOP_LITE>, <&cru DCLK_VOP_LITE>,
<&cru HCLK_VOP_LITE>;
clock-names = "aclk_vop", "dclk_vop", "hclk_vop";
resets = <&cru SRST_VOP1_AXI>, <&cru SRST_VOP1_DCLK>,
<&cru SRST_VOP1_AHB>;
reset-names = "axi", "ahb", "dclk";
power-domains = <&power RK3366_PD_VIO>;
iommus = <&vopl_mmu>;
status = "disabled";
vopl_out: port {
#address-cells = <1>;
#size-cells = <0>;
vopl_out_dsi: endpoint@0 {
reg = <0>;
remote-endpoint = <&dsi_in_vopl>;
};
vopl_out_lvds: endpoint@1 {
reg = <1>;
remote-endpoint = <&lvds_in_vopl>;
};
};
};
vopl_mmu: iommu@ff8f0f00 {
compatible = "rockchip,iommu";
reg = <0x0 0xff8f0f00 0x0 0x100>;
interrupts = <GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>;
interrupt-names = "vopl_mmu";
clocks = <&cru ACLK_VOP_LITE>, <&cru HCLK_VOP_LITE>;
clock-names = "aclk", "hclk";
power-domains = <&power RK3366_PD_VIO>;
#iommu-cells = <0>;
status = "disabled";
};
iep: iep@ff900000 {
compatible = "rockchip,iep";
iommu_enabled = <1>;
iommus = <&iep_mmu>;
reg = <0x0 0xff900000 0x0 0x800>;
interrupts = <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&cru ACLK_IEP>, <&cru HCLK_IEP>;
clock-names = "aclk_iep", "hclk_iep";
power-domains = <&power RK3366_PD_VIO>;
allocator = <1>;
version = <2>;
status = "disabled";
};
iep_mmu: iommu@ff900800 {
compatible = "rockchip,iommu";
reg = <0x0 0xff900800 0x0 0x100>;
interrupts = <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>;
interrupt-names = "iep_mmu";
power-domains = <&power RK3366_PD_VIO>;
#iommu-cells = <0>;
status = "disabled";
};
rga: rga@ff920000 {
compatible = "rockchip,rga2";
dev_mode = <1>;
reg = <0x0 0xff920000 0x0 0x1000>;
interrupts = <GIC_SPI 18 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&cru ACLK_RGA>, <&cru HCLK_RGA>, <&cru SCLK_RGA>;
clock-names = "aclk_rga", "hclk_rga", "clk_rga";
power-domains = <&power RK3366_PD_VIO>;
dma-coherent;
status = "disabled";
};
vopb: vop@ff930000 {
compatible = "rockchip,rk3366-vop";
reg = <0x0 0xff930000 0x0 0x1ffc>;
interrupts = <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&cru ACLK_VOP_FULL>, <&cru DCLK_VOP_FULL>,
<&cru HCLK_VOP_FULL>;
clock-names = "aclk_vop", "dclk_vop", "hclk_vop";
power-domains = <&power RK3366_PD_VIO>;
resets = <&cru SRST_VOP0_AXI>, <&cru SRST_VOP0_DCLK>,
<&cru SRST_VOP0_AHB>;
reset-names = "axi", "ahb", "dclk";
iommus = <&vopb_mmu>;
status = "disabled";
vopb_out: port {
#address-cells = <1>;
#size-cells = <0>;
vopb_out_dsi: endpoint@0 {
reg = <0>;
remote-endpoint = <&dsi_in_vopb>;
};
vopb_out_lvds: endpoint@1 {
reg = <1>;
remote-endpoint = <&lvds_in_vopb>;
};
vopb_out_hdmi: endpoint@2 {
reg = <2>;
remote-endpoint = <&hdmi_in_vopb>;
};
};
};
vopb_mmu: iommu@ff932400 {
compatible = "rockchip,iommu";
reg = <0x0 0xff932400 0x0 0x100>;
interrupts = <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>;
interrupt-names = "vop_mmu";
clocks = <&cru ACLK_VOP_FULL>, <&cru HCLK_VOP_FULL>;
clock-names = "aclk", "hclk";
power-domains = <&power RK3366_PD_VIO>;
#iommu-cells = <0>;
status = "disabled";
};
dsi: dsi@ff960000 {
compatible = "rockchip,rk3366-mipi-dsi";
reg = <0x0 0xff960000 0x0 0x4000>;
interrupts = <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&cru PCLK_MIPI_DSI0>, <&mipi_dphy>;
clock-names = "pclk", "hs_clk";
resets = <&cru SRST_MIPIDSI0>;
reset-names = "apb";
phys = <&mipi_dphy>;
phy-names = "mipi_dphy";
power-domains = <&power RK3366_PD_VIO>;
rockchip,grf = <&grf>;
#address-cells = <1>;
#size-cells = <0>;
status = "disabled";
ports {
port {
#address-cells = <1>;
#size-cells = <0>;
dsi_in_vopb: endpoint@0 {
reg = <0>;
remote-endpoint = <&vopb_out_dsi>;
};
dsi_in_vopl: endpoint@1 {
reg = <1>;
remote-endpoint = <&vopl_out_dsi>;
};
};
};
};
mipi_dphy: mipi-dphy@ff968000 {
compatible = "rockchip,rk3366-mipi-dphy";
reg = <0x0 0xff968000 0x0 0x4000>;
clocks = <&cru SCLK_MIPIDSI_24M>, <&cru PCLK_DPHYTX>;
clock-names = "ref", "pclk";
clock-output-names = "mipi_dphy_pll";
#clock-cells = <0>;
resets = <&cru SRST_MIPIDPHYTX>;
reset-names = "apb";
power-domains = <&power RK3366_PD_VIO>;
rockchip,grf = <&grf>;
#phy-cells = <0>;
status = "disabled";
};
lvds: lvds@ff968000 {
compatible = "rockchip,rk3366-lvds";
reg = <0x0 0xff968000 0x0 0x4000>, <0x0 0xff960000 0x0 0x100>;
reg-names = "mipi_lvds_phy", "mipi_lvds_ctl";
clocks = <&cru PCLK_DPHYTX>, <&cru PCLK_MIPI_DSI0>;
clock-names = "pclk_lvds", "pclk_lvds_ctl";
power-domains = <&power RK3366_PD_VIO>;
rockchip,grf = <&grf>;
status = "disabled";
ports {
#address-cells = <1>;
#size-cells = <0>;
port@0 {
reg = <0>;
#address-cells = <1>;
#size-cells = <0>;
lvds_in_vopb: endpoint@0 {
reg = <0>;
remote-endpoint = <&vopb_out_lvds>;
};
lvds_in_vopl: endpoint@1 {
reg = <1>;
remote-endpoint = <&vopl_out_lvds>;
};
};
};
};
hdmi: hdmi@ff980000 {
compatible = "rockchip,rk3366-dw-hdmi";
reg = <0x0 0xff980000 0x0 0x20000>;
reg-io-width = <4>;
interrupts = <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&cru PCLK_HDMI_CTRL>, <&cru SCLK_HDMI_HDCP>,
<&cru SCLK_HDMI_CEC>, <&cru DCLK_HDMIPHY>;
clock-names = "iahb", "isfr", "cec", "dclk";
pinctrl-names = "default";
pinctrl-0 = <&hdmii2c_xfer &hdmi_cec>;
resets = <&cru SRST_HDMI>;
reset-names = "hdmi";
//power-domains = <&power RK3366_PD_VIO>;
rockchip,grf = <&grf>;
status = "disabled";
ports {
port {
#address-cells = <1>;
#size-cells = <0>;
hdmi_in_vopb: endpoint@0 {
reg = <0>;
remote-endpoint = <&vopb_out_hdmi>;
};
};
};
};
vpu: vpu_service@ff9a0000 {
compatible = "rockchip,vpu_service";
rockchip,grf = <&grf>;
iommu_enabled = <1>;
iommus = <&vpu_mmu>;
reg = <0x0 0xff9a0000 0x0 0x800>;
interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>;
interrupt-names = "irq_dec", "irq_enc";
clocks = <&cru ACLK_VIDEO>, <&cru HCLK_VIDEO>;
clock-names = "aclk_vcodec", "hclk_vcodec";
power-domains = <&power RK3366_PD_VPU>;
resets = <&cru SRST_VIDEO_AHB>, <&cru SRST_VIDEO_AXI>;
reset-names = "video_h", "video_a";
name = "vpu_service";
dev_mode = <0>;
/* 0 means ion, 1 means drm */
allocator = <1>;
status = "disabled";
};
vpu_mmu: iommu@ff9a0800 {
compatible = "rockchip,iommu";
reg = <0x0 0xff9a0800 0x0 0x100>;
interrupts = <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>;
interrupt-names = "vpu_mmu";
clocks = <&cru ACLK_VIDEO>, <&cru HCLK_VIDEO>;
clock-names = "aclk", "hclk";
power-domains = <&power RK3366_PD_VPU>;
#iommu-cells = <0>;
status = "disabled";
};
rkvdec: rkvdec@ff9b0000 {
compatible = "rockchip,rkvdec";
rockchip,grf = <&grf>;
iommus = <&vdec_mmu>;
iommu_enabled = <1>;
reg = <0x0 0xff9b0000 0x0 0x400>;
interrupts = <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>;
interrupt-names = "irq_dec";
clocks = <&cru ACLK_RKVDEC>, <&cru HCLK_RKVDEC>,<&cru SCLK_HEVC_CABAC>,<&cru SCLK_HEVC_CORE>;
clock-names = "aclk_vcodec", "hclk_vcodec", "clk_cabac", "clk_core";
power-domains = <&power RK3366_PD_RKVDEC>;
resets = <&cru SRST_RKVDEC_AHB>, <&cru SRST_VIDEO_AXI>;
reset-names = "video_h", "video_a";
dev_mode = <2>;
name = "rkvdec";
/* 0 means ion, 1 means drm */
allocator = <1>;
status = "disabled";
};
vdec_mmu: iommu@ff9b0480 {
compatible = "rockchip,iommu";
reg = <0x0 0xff9b0480 0x0 0x40>,
<0x0 0xff9b04c0 0x0 0x40>;
interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>;
interrupt-names = "vdec_mmu";
clocks = <&cru ACLK_RKVDEC>, <&cru HCLK_RKVDEC>;
clock-names = "aclk", "hclk";
power-domains = <&power RK3366_PD_RKVDEC>;
#iommu-cells = <0>;
status = "disabled";
};
qos_iep: qos@ffad0000 {
compatible = "syscon";
reg = <0x0 0xffad0000 0x0 0x20>;
};
qos_isp_r0: qos@ffad0080 {
compatible = "syscon";
reg = <0x0 0xffad0080 0x0 0x20>;
};
qos_isp_r1: qos@ffad0100 {
compatible = "syscon";
reg = <0x0 0xffad0100 0x0 0x20>;
};
qos_isp_w0: qos@ffad0180 {
compatible = "syscon";
reg = <0x0 0xffad0180 0x0 0x20>;
};
qos_isp_w1: qos@ffad0200 {
compatible = "syscon";
reg = <0x0 0xffad0200 0x0 0x20>;
};
qos_vop0_w: qos@ffad0300 {
compatible = "syscon";
reg = <0x0 0xffad0300 0x0 0x20>;
};
qos_rga_r: qos@ffad0380 {
compatible = "syscon";
reg = <0x0 0xffad0380 0x0 0x20>;
};
qos_rga_w: qos@ffad0400 {
compatible = "syscon";
reg = <0x0 0xffad0400 0x0 0x20>;
};
qos_vop0_r: qos@ffad0480 {
compatible = "syscon";
reg = <0x0 0xffad0480 0x0 0x20>;
};
qos_vop1_r: qos@ffad0580 {
compatible = "syscon";
reg = <0x0 0xffad0580 0x0 0x20>;
};
qos_hdcp: qos@ffad0600 {
compatible = "syscon";
reg = <0x0 0xffad0600 0x0 0x20>;
};
qos_rkvdec_r: qos@ffae0000 {
compatible = "syscon";
reg = <0x0 0xffae0000 0x0 0x20>;
};
qos_rkvdec_w: qos@ffae0080 {
compatible = "syscon";
reg = <0x0 0xffae0080 0x0 0x20>;
};
qos_vpu_r: qos@ffae0100 {
compatible = "syscon";
reg = <0x0 0xffae0100 0x0 0x20>;
};
qos_vpu_w: qos@ffae0180 {
compatible = "syscon";
reg = <0x0 0xffae0180 0x0 0x20>;
};
qos_gpu: qos@ffaf0000 {
compatible = "syscon";
reg = <0x0 0xffaf0000 0x0 0x20>;
};
pinctrl: pinctrl {
compatible = "rockchip,rk3366-pinctrl";
rockchip,grf = <&grf>;
rockchip,pmu = <&pmugrf>;
#address-cells = <0x2>;
#size-cells = <0x2>;
ranges;
gpio0: gpio0@ff750000 {
compatible = "rockchip,gpio-bank";
reg = <0x0 0xff750000 0x0 0x100>;
clocks = <&cru PCLK_GPIO0>;
interrupts = <GIC_SPI 81 IRQ_TYPE_LEVEL_HIGH>;
gpio-controller;
#gpio-cells = <0x2>;
interrupt-controller;
#interrupt-cells = <0x2>;
};
gpio1: gpio1@ff780000 {
compatible = "rockchip,gpio-bank";
reg = <0x0 0xff758000 0x0 0x100>;
clocks = <&cru PCLK_GPIO1>;
interrupts = <GIC_SPI 82 IRQ_TYPE_LEVEL_HIGH>;
gpio-controller;
#gpio-cells = <0x2>;
interrupt-controller;
#interrupt-cells = <0x2>;
};
gpio2: gpio2@ff790000 {
compatible = "rockchip,gpio-bank";
reg = <0x0 0xff790000 0x0 0x100>;
clocks = <&cru PCLK_GPIO2>;
interrupts = <GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>;
gpio-controller;
#gpio-cells = <0x2>;
interrupt-controller;
#interrupt-cells = <0x2>;
};
gpio3: gpio3@ff7a0000 {
compatible = "rockchip,gpio-bank";
reg = <0x0 0xff7a0000 0x0 0x100>;
clocks = <&cru PCLK_GPIO3>;
interrupts = <GIC_SPI 84 IRQ_TYPE_LEVEL_HIGH>;
gpio-controller;
#gpio-cells = <0x2>;
interrupt-controller;
#interrupt-cells = <0x2>;
};
gpio4: gpio4@ff7b0000 {
compatible = "rockchip,gpio-bank";
reg = <0x0 0xff7b0000 0x0 0x100>;
clocks = <&cru PCLK_GPIO4>;
interrupts = <GIC_SPI 85 IRQ_TYPE_LEVEL_HIGH>;
gpio-controller;
#gpio-cells = <0x2>;
interrupt-controller;
#interrupt-cells = <0x2>;
};
gpio5: gpio5@ff7c0000 {
compatible = "rockchip,gpio-bank";
reg = <0x0 0xff7c0000 0x0 0x100>;
clocks = <&cru PCLK_GPIO5>;
interrupts = <GIC_SPI 87 IRQ_TYPE_LEVEL_HIGH>;
gpio-controller;
#gpio-cells = <0x2>;
interrupt-controller;
#interrupt-cells = <0x2>;
};
pcfg_pull_up: pcfg-pull-up {
bias-pull-up;
};
pcfg_pull_down: pcfg-pull-down {
bias-pull-down;
};
pcfg_pull_none: pcfg-pull-none {
bias-disable;
};
pcfg_pull_none_12ma: pcfg-pull-none-12ma {
bias-disable;
drive-strength = <12>;
};
emmc {
emmc_clk: emmc-clk {
rockchip,pins =
<3 4 RK_FUNC_2 &pcfg_pull_none>;
};
emmc_cmd: emmc-cmd {
rockchip,pins =
<2 26 RK_FUNC_2 &pcfg_pull_up>;
};
emmc_pwr: emmc-pwr {
rockchip,pins =
<2 27 RK_FUNC_2 &pcfg_pull_up>;
};
emmc_bus1: emmc-bus1 {
rockchip,pins =
<2 18 RK_FUNC_2 &pcfg_pull_up>;
};
emmc_bus4: emmc-bus4 {
rockchip,pins =
<2 18 RK_FUNC_2 &pcfg_pull_up>,
<2 19 RK_FUNC_2 &pcfg_pull_up>,
<2 20 RK_FUNC_2 &pcfg_pull_up>,
<2 21 RK_FUNC_2 &pcfg_pull_up>;
};
emmc_bus8: emmc-bus8 {
rockchip,pins =
<2 18 RK_FUNC_2 &pcfg_pull_up>,
<2 19 RK_FUNC_2 &pcfg_pull_up>,
<2 20 RK_FUNC_2 &pcfg_pull_up>,
<2 21 RK_FUNC_2 &pcfg_pull_up>,
<2 22 RK_FUNC_2 &pcfg_pull_up>,
<2 23 RK_FUNC_2 &pcfg_pull_up>,
<2 24 RK_FUNC_2 &pcfg_pull_up>,
<2 25 RK_FUNC_2 &pcfg_pull_up>;
};
};
sdmmc {
sdmmc_cd: sdmmc-cd {
rockchip,pins = <0 9 RK_FUNC_1 &pcfg_pull_up>;
};
sdmmc_bus1: sdmmc-bus1 {
rockchip,pins = <5 0 RK_FUNC_1 &pcfg_pull_up>;
};
sdmmc_bus4: sdmmc-bus4 {
rockchip,pins = <5 0 RK_FUNC_1 &pcfg_pull_up>,
<5 1 RK_FUNC_1 &pcfg_pull_up>,
<5 2 RK_FUNC_1 &pcfg_pull_up>,
<5 3 RK_FUNC_1 &pcfg_pull_up>;
};
sdmmc_clk: sdmmc-clk {
rockchip,pins = <5 4 RK_FUNC_1 &pcfg_pull_none>;
};
sdmmc_cmd: sdmmc-cmd {
rockchip,pins = <5 5 RK_FUNC_1 &pcfg_pull_up>;
};
};
sdio {
sdio_bus1: sdio-bus1 {
rockchip,pins = <3 12 RK_FUNC_1 &pcfg_pull_up>;
};
sdio_bus4: sdio-bus4 {
rockchip,pins = <3 12 RK_FUNC_1 &pcfg_pull_up>,
<3 13 RK_FUNC_1 &pcfg_pull_up>,
<3 14 RK_FUNC_1 &pcfg_pull_up>,
<3 15 RK_FUNC_1 &pcfg_pull_up>;
};
sdio_cmd: sdio-cmd {
rockchip,pins = <3 16 RK_FUNC_1 &pcfg_pull_up>;
};
sdio_clk: sdio-clk {
rockchip,pins = <3 17 RK_FUNC_1 &pcfg_pull_none>;
};
sdio_cd: sdio-cd {
rockchip,pins = <3 18 RK_FUNC_1 &pcfg_pull_up>;
};
sdio_wp: sdio-wp {
rockchip,pins = <3 19 RK_FUNC_1 &pcfg_pull_up>;
};
sdio_int: sdio-int {
rockchip,pins = <3 20 RK_FUNC_1 &pcfg_pull_up>;
};
sdio_pwr: sdio-pwr {
rockchip,pins = <3 21 RK_FUNC_1 &pcfg_pull_up>;
};
};
hdmi_i2c {
hdmii2c_xfer: hdmii2c-xfer {
rockchip,pins =
<5 13 RK_FUNC_2 &pcfg_pull_none>,
<5 14 RK_FUNC_2 &pcfg_pull_none>;
};
};
hdmi_pin {
hdmi_cec: hdmi-cec {
rockchip,pins =
<5 12 RK_FUNC_1 &pcfg_pull_none>;
};
};
i2c0 {
i2c0_xfer: i2c0-xfer {
rockchip,pins =
<0 3 RK_FUNC_1 &pcfg_pull_none>,
<0 4 RK_FUNC_1 &pcfg_pull_none>;
};
};
i2c1 {
i2c1_xfer: i2c1-xfer {
rockchip,pins =
<4 25 RK_FUNC_1 &pcfg_pull_none>,
<4 26 RK_FUNC_1 &pcfg_pull_none>;
};
};
i2c2 {
i2c2_xfer: i2c2-xfer {
rockchip,pins =
<5 15 RK_FUNC_2 &pcfg_pull_none>,
<5 16 RK_FUNC_2 &pcfg_pull_none>;
};
i2c2_gpio: i2c2-gpio {
rockchip,pins =
<5 15 RK_FUNC_GPIO &pcfg_pull_none>,
<5 16 RK_FUNC_GPIO &pcfg_pull_none>;
};
};
i2c3 {
i2c3_xfer: i2c3-xfer {
rockchip,pins =
<2 16 RK_FUNC_2 &pcfg_pull_none>,
<2 17 RK_FUNC_2 &pcfg_pull_none>;
};
};
i2c4 {
i2c4_xfer: i2c4-xfer {
rockchip,pins =
<5 8 RK_FUNC_1 &pcfg_pull_none>,
<5 9 RK_FUNC_1 &pcfg_pull_none>;
};
i2c4_gpio: i2c4-gpio {
rockchip,pins =
<5 8 RK_FUNC_GPIO &pcfg_pull_none>,
<5 9 RK_FUNC_GPIO &pcfg_pull_none>;
};
};
i2c5 {
i2c5_xfer: i2c5-xfer {
rockchip,pins =
<5 13 RK_FUNC_1 &pcfg_pull_none>,
<5 14 RK_FUNC_1 &pcfg_pull_none>;
};
i2c5_gpio: i2c5-gpio {
rockchip,pins =
<5 13 RK_FUNC_GPIO &pcfg_pull_none>,
<5 14 RK_FUNC_GPIO &pcfg_pull_none>;
};
};
i2s {
i2s_8ch_bus: i2s-8ch-bus {
rockchip,pins =
<4 16 RK_FUNC_1 &pcfg_pull_none>,
<4 17 RK_FUNC_1 &pcfg_pull_none>,
<4 18 RK_FUNC_1 &pcfg_pull_none>,
<4 19 RK_FUNC_1 &pcfg_pull_none>,
<4 20 RK_FUNC_1 &pcfg_pull_none>,
<4 21 RK_FUNC_1 &pcfg_pull_none>,
<4 22 RK_FUNC_1 &pcfg_pull_none>,
<4 23 RK_FUNC_1 &pcfg_pull_none>,
<4 24 RK_FUNC_1 &pcfg_pull_none>;
};
};
spdif {
spdif_bus: spdif-bus {
rockchip,pins =
<5 19 RK_FUNC_1 &pcfg_pull_none>;
};
};
spi0 {
spi0_clk: spi0-clk {
rockchip,pins =
<2 29 RK_FUNC_2 &pcfg_pull_up>;
};
spi0_cs0: spi0-cs0 {
rockchip,pins =
<2 24 RK_FUNC_3 &pcfg_pull_up>;
};
spi0_cs1: spi0-cs1 {
rockchip,pins =
<2 25 RK_FUNC_3 &pcfg_pull_up>;
};
spi0_tx: spi0-tx {
rockchip,pins =
<2 23 RK_FUNC_3 &pcfg_pull_up>;
};
spi0_rx: spi0-rx {
rockchip,pins =
<2 22 RK_FUNC_3 &pcfg_pull_up>;
};
};
spi1 {
spi1_clk: spi1-clk {
rockchip,pins =
<2 4 RK_FUNC_3 &pcfg_pull_up>;
};
spi1_cs0: spi1-cs0 {
rockchip,pins =
<2 5 RK_FUNC_3 &pcfg_pull_up>;
};
spi1_tx: spi1-tx {
rockchip,pins =
<2 6 RK_FUNC_3 &pcfg_pull_up>;
};
spi1_rx: spi1-rx {
rockchip,pins =
<2 7 RK_FUNC_3 &pcfg_pull_up>;
};
};
scr {
scr_clk: scr-clk {
rockchip,pins =
<5 8 RK_FUNC_2 &pcfg_pull_none>;
};
scr_io: scr-io {
rockchip,pins =
<5 9 RK_FUNC_2 &pcfg_pull_up>;
};
scr_rst: scr-rst {
rockchip,pins =
<5 10 RK_FUNC_1 &pcfg_pull_none>;
};
scr_detect: scr-detect {
rockchip,pins =
<5 11 RK_FUNC_1 &pcfg_pull_none>;
};
};
uart0 {
uart0_xfer: uart0-xfer {
rockchip,pins =
<3 8 RK_FUNC_1 &pcfg_pull_up>,
<3 9 RK_FUNC_1 &pcfg_pull_none>;
};
uart0_cts: uart0-cts {
rockchip,pins =
<3 10 RK_FUNC_1 &pcfg_pull_none>;
};
uart0_rts: uart0-rts {
rockchip,pins =
<3 11 RK_FUNC_1 &pcfg_pull_none>;
};
};
uart2_t0 {
uart2_t0_xfer: uart2_t0-xfer {
rockchip,pins =
<0 22 RK_FUNC_1 &pcfg_pull_up>,
<0 21 RK_FUNC_1 &pcfg_pull_none>;
};
/* no rts / cts for uart2 */
};
uart2_t1 {
uart2_t1_xfer: uart2_t1-xfer {
rockchip,pins =
<5 0 RK_FUNC_2 &pcfg_pull_up>,
<5 1 RK_FUNC_2 &pcfg_pull_none>;
};
/* no rts / cts for uart2 */
};
uart2_t2 {
uart2_t2_xfer: uart2_t2-xfer {
rockchip,pins =
<5 14 RK_FUNC_3 &pcfg_pull_up>,
<5 13 RK_FUNC_3 &pcfg_pull_none>;
};
/* no rts / cts for uart2 */
};
uart3 {
uart3_xfer: uart3-xfer {
rockchip,pins =
<5 15 RK_FUNC_1 &pcfg_pull_up>,
<5 16 RK_FUNC_1 &pcfg_pull_none>;
};
uart3_cts: uart3-cts {
rockchip,pins =
<5 17 RK_FUNC_1 &pcfg_pull_none>;
};
uart3_rts: uart3-rts {
rockchip,pins =
<5 18 RK_FUNC_1 &pcfg_pull_none>;
};
};
pwm0 {
pwm0_pin: pwm0-pin {
rockchip,pins =
<0 8 RK_FUNC_1 &pcfg_pull_none>;
};
};
pwm1 {
pwm1_pin: pwm1-pin {
rockchip,pins =
<1 6 RK_FUNC_2 &pcfg_pull_none>;
};
};
pwm2_t0 {
pwm2_t0_pin: pwm2_t0-pin {
rockchip,pins =
<2 15 RK_FUNC_3 &pcfg_pull_none>;
};
};
pwm2_t1 {
pwm2_t1_pin: pwm2_t1-pin {
rockchip,pins =
<5 17 RK_FUNC_2 &pcfg_pull_none>;
};
};
pwm3_t0 {
pwm3_t0_pin: pwm3_t0-pin {
rockchip,pins =
<1 0 RK_FUNC_2 &pcfg_pull_none>;
};
};
pwm3_t1 {
pwm3_t1_pin: pwm3_t1-pin {
rockchip,pins =
<0 21 RK_FUNC_2 &pcfg_pull_none>;
};
};
pwm3_t2 {
pwm3_t2_pin: pwm3_t2-pin {
rockchip,pins =
<5 18 RK_FUNC_2 &pcfg_pull_none>;
};
};
lcdc {
lcdc_lcdc: lcdc-lcdc {
rockchip,pins =
<0 24 RK_FUNC_2 &pcfg_pull_none>, /* HSYNC */
<0 25 RK_FUNC_2 &pcfg_pull_none>, /* VSYNC */
<0 26 RK_FUNC_1 &pcfg_pull_none>, /* LCDC_D10 */
<0 27 RK_FUNC_1 &pcfg_pull_none>, /* LCDC_D11 */
<0 28 RK_FUNC_1 &pcfg_pull_none>, /* LCDC_D12 */
<0 29 RK_FUNC_1 &pcfg_pull_none>, /* LCDC_D13 */
<0 30 RK_FUNC_1 &pcfg_pull_none>, /* LCDC_D14 */
<0 31 RK_FUNC_1 &pcfg_pull_none>, /* LCDC_D15 */
<1 0 RK_FUNC_1 &pcfg_pull_none>, /* LCDC_D16 */
<1 1 RK_FUNC_1 &pcfg_pull_none>, /* LCDC_D17 */
<1 2 RK_FUNC_1 &pcfg_pull_none>, /* LCDC_D18 */
<1 3 RK_FUNC_1 &pcfg_pull_none>, /* LCDC_D19 */
<1 4 RK_FUNC_1 &pcfg_pull_none>, /* LCDC_D20 */
<1 5 RK_FUNC_1 &pcfg_pull_none>, /* LCDC_D21 */
<1 6 RK_FUNC_1 &pcfg_pull_none>, /* LCDC_D22 */
<1 7 RK_FUNC_1 &pcfg_pull_none>, /* LCDC_D23 */
<1 8 RK_FUNC_1 &pcfg_pull_none>, /* DEN */
<1 9 RK_FUNC_1 &pcfg_pull_none>; /* DCLK */
};
lcdc_gpio: lcdc-gpio {
rockchip,pins =
<0 24 RK_FUNC_GPIO &pcfg_pull_none>, /* HSYNC */
<0 25 RK_FUNC_GPIO &pcfg_pull_none>, /* VSYNC */
<0 26 RK_FUNC_GPIO &pcfg_pull_none>, /* LCDC_D10 */
<0 27 RK_FUNC_GPIO &pcfg_pull_none>, /* LCDC_D11 */
<0 28 RK_FUNC_GPIO &pcfg_pull_none>, /* LCDC_D12 */
<0 29 RK_FUNC_GPIO &pcfg_pull_none>, /* LCDC_D13 */
<0 30 RK_FUNC_GPIO &pcfg_pull_none>, /* LCDC_D14 */
<0 31 RK_FUNC_GPIO &pcfg_pull_none>, /* LCDC_D15 */
<1 0 RK_FUNC_GPIO &pcfg_pull_none>, /* LCDC_D16 */
<1 1 RK_FUNC_GPIO &pcfg_pull_none>, /* LCDC_D17 */
<1 2 RK_FUNC_GPIO &pcfg_pull_none>, /* LCDC_D18 */
<1 3 RK_FUNC_GPIO &pcfg_pull_none>, /* LCDC_D19 */
<1 4 RK_FUNC_GPIO &pcfg_pull_none>, /* LCDC_D20 */
<1 5 RK_FUNC_GPIO &pcfg_pull_none>, /* LCDC_D21 */
<1 6 RK_FUNC_GPIO &pcfg_pull_none>, /* LCDC_D22 */
<1 7 RK_FUNC_GPIO &pcfg_pull_none>, /* LCDC_D23 */
<1 8 RK_FUNC_GPIO &pcfg_pull_none>, /* DEN */
<1 9 RK_FUNC_GPIO &pcfg_pull_none>; /* DCLK */
};
};
gmac {
rgmii_pins: rgmii-pins {
rockchip,pins =
/* mac_rxd3 */
<2 7 RK_FUNC_1 &pcfg_pull_none>,
/* mac_rxd2 */
<2 6 RK_FUNC_1 &pcfg_pull_none>,
/* mac_txd3 */
<2 5 RK_FUNC_1 &pcfg_pull_none_12ma>,
/* mac_txd2 */
<2 4 RK_FUNC_1 &pcfg_pull_none_12ma>,
/* mac_rxd1 */
<2 3 RK_FUNC_1 &pcfg_pull_none>,
/* mac_rxd0 */
<2 2 RK_FUNC_1 &pcfg_pull_none>,
/* mac_txd1 */
<2 1 RK_FUNC_1 &pcfg_pull_none_12ma>,
/* mac_txd0 */
<2 0 RK_FUNC_1 &pcfg_pull_none>,
/* mac_txclkout */
<2 17 RK_FUNC_1 &pcfg_pull_none_12ma>,
/* mac_crs */
/* <2 15 RK_FUNC_1 &pcfg_pull_none>, */
/* mac_rxclkin */
<2 14 RK_FUNC_1 &pcfg_pull_none>,
/* mac_mdio */
<2 13 RK_FUNC_1 &pcfg_pull_none>,
/* mac_txen */
<2 12 RK_FUNC_1 &pcfg_pull_none_12ma>,
/* mac_clk */
<2 11 RK_FUNC_1 &pcfg_pull_none>,
/* mac_rxer */
/* <2 10 RK_FUNC_1 &pcfg_pull_none>, */
/* mac_rxdv */
<2 9 RK_FUNC_1 &pcfg_pull_none>,
/* mac_mdc */
<2 8 RK_FUNC_1 &pcfg_pull_none>;
};
rmii_pins: rmii-pins {
rockchip,pins =
/* mac_rxd1 */
<2 3 RK_FUNC_1 &pcfg_pull_none>,
/* mac_rxd0 */
<2 2 RK_FUNC_1 &pcfg_pull_none>,
/* mac_txd1 */
<2 1 RK_FUNC_1 &pcfg_pull_none>,
/* mac_txd0 */
<2 0 RK_FUNC_1 &pcfg_pull_none>,
/* mac_crs */
/* <2 15 RK_FUNC_1 &pcfg_pull_none>, */
/* mac_rxclkin */
<2 14 RK_FUNC_1 &pcfg_pull_none>,
/* mac_mdio */
<2 13 RK_FUNC_1 &pcfg_pull_none>,
/* mac_txen */
<2 12 RK_FUNC_1 &pcfg_pull_none>,
/* mac_clk */
<2 11 RK_FUNC_1 &pcfg_pull_none>,
/* mac_rxer */
/* <2 10 RK_FUNC_1 &pcfg_pull_none>, */
/* mac_rxdv */
<2 9 RK_FUNC_1 &pcfg_pull_none>,
/* mac_mdc */
<2 8 RK_FUNC_1 &pcfg_pull_none>;
};
};
eth_phy {
eth_phy_pwr: eth-phy-pwr {
rockchip,pins =
<0 25 RK_FUNC_GPIO &pcfg_pull_none>;
};
};
tsadc_pin {
tsadc_gpio: tsadc-gpio {
rockchip,pins =
<0 22 RK_FUNC_GPIO &pcfg_pull_none>;
};
tsadc_int: tsadc-int {
rockchip,pins =
<0 22 RK_FUNC_2 &pcfg_pull_none>;
};
};
usb2 {
host_vbus_drv: host-vbus-drv {
rockchip,pins =
<0 16 RK_FUNC_GPIO &pcfg_pull_none>;
};
};
};
gpu: gpu@ffa30000 {
compatible = "arm,malit764",
"arm,malit76x",
"arm,malit7xx",
"arm,mali-midgard";
reg = <0x0 0xffa30000 0 0x10000>;
interrupts = <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>;
interrupt-names = "GPU", "MMU", "JOB";
clocks = <&cru ACLK_GPU>;
clock-names = "clk_mali";
#cooling-cells = <2>; /* min followed by max */
power-domains = <&power RK3366_PD_GPU>;
operating-points-v2 = <&gpu_opp_table>;
status = "disabled";
power_model {
compatible = "arm,mali-simple-power-model";
voltage = <900>;
frequency = <500>;
static-power = <300>;
dynamic-power = <1780>;
ts = <32000 4700 (-80) 2>;
thermal-zone = "gpu-thermal";
};
};
gpu_opp_table: gpu_opp_table {
compatible = "operating-points-v2";
opp-shared;
opp-96000000 {
opp-hz = /bits/ 64 <96000000>;
opp-microvolt = <1100000>;
};
opp-192000000 {
opp-hz = /bits/ 64 <192000000>;
opp-microvolt = <1100000>;
};
opp-288000000 {
opp-hz = /bits/ 64 <288000000>;
opp-microvolt = <1100000>;
};
opp-375000000 {
opp-hz = /bits/ 64 <375000000>;
opp-microvolt = <1125000>;
};
opp-480000000 {
opp-hz = /bits/ 64 <480000000>;
opp-microvolt = <1200000>;
};
};
};