关键词：rk3188-clocks.dtsi ,linux_3.10,rockchip,dts
dts — rk3188-clocks.dtsi
/*
* Copyright (C) 2013 ROCKCHIP, Inc.
* Author: chenxing <chenxing@rock-chips.com>
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; either version 2 of the License, or
* (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*/
#include <dt-bindings/clock/rockchip,rk3188.h>
/{
clocks {
compatible = "rockchip,rk-clocks";
#address-cells = <1>;
#size-cells = <1>;
ranges = <0x0 0x20000000 0x0100>;
fixed_rate_cons {
compatible = "rockchip,rk-fixed-rate-cons";
xin24m: xin24m {
compatible = "fixed-clock";
#clock-cells = <0>;
clock-output-names = "xin24m";
clock-frequency = <24000000>;
};
xin12m: xin12m {
compatible = "fixed-clock";
#clock-cells = <0>;
clocks = <&xin24m>;
clock-output-names = "xin12m";
clock-frequency = <12000000>;
};
dummy: dummy {
compatible = "fixed-clock";
#clock-cells = <0>;
clock-output-names = "dummy";
clock-frequency = <0>;
};
rmii_clkin: rmii_clkin {
compatible = "fixed-clock";
#clock-cells = <0>;
clock-output-names = "rmii_clkin";
clock-frequency = <0>;
};
clk_hsadc_ext: clk_hsadc_ext {
compatible = "fixed-clock";
#clock-cells = <0>;
clock-output-names = "clk_hsadc_ext";
clock-frequency = <0>;
};
clk_cif_in: clk_cif_in {
compatible = "fixed-clock";
#clock-cells = <0>;
clock-output-names = "clk_cif_in";
clock-frequency = <0>;
};
};
fixed_factor_cons {
compatible = "rockchip,rk-fixed-factor-cons";
otgphy0_480m: otgphy0_480m {
compatible = "fixed-factor-clock";
clocks = <&clk_gates1 5>;
clock-output-names = "otgphy0_480m";
clock-div = <1>;
clock-mult = <20>;
#clock-cells = <0>;
};
otgphy1_480m: otgphy1_480m {
compatible = "fixed-factor-clock";
clocks = <&clk_gates1 6>;
clock-output-names = "otgphy1_480m";
clock-div = <1>;
clock-mult = <20>;
#clock-cells = <0>;
};
};
clock_regs {
compatible = "rockchip,rk-clock-regs";
reg = <0x0000 0x3ff>;
#address-cells = <1>;
#size-cells = <1>;
ranges;
/* PLL control regs */
pll_cons {
compatible = "rockchip,rk-pll-cons";
#address-cells = <1>;
#size-cells = <1>;
ranges ;
clk_apll: pll-clk@0000 {
compatible = "rockchip,rk3188-pll-clk";
reg = <0x0000 0x10>;
mode-reg = <0x0040 0>;
status-reg = <0x00ac 6>;
clocks = <&xin24m>;
clock-output-names = "clk_apll";
rockchip,pll-type = <CLK_PLL_3188_APLL>;
#clock-cells = <0>;
};
clk_dpll: pll-clk@0010 {
compatible = "rockchip,rk3188-pll-clk";
reg = <0x0010 0x10>;
mode-reg = <0x0040 4>;
status-reg = <0x00ac 5>;
clocks = <&xin24m>;
clock-output-names = "clk_dpll";
rockchip,pll-type = <CLK_PLL_3188>;
#clock-cells = <0>;
};
clk_cpll: pll-clk@0020 {
compatible = "rockchip,rk3188-pll-clk";
reg = <0x0020 0x10>;
mode-reg = <0x0040 8>;
status-reg = <0x00ac 7>;
clocks = <&xin24m>;
clock-output-names = "clk_cpll";
rockchip,pll-type = <CLK_PLL_3188>;
#clock-cells = <0>;
#clock-init-cells = <1>;
};
clk_gpll: pll-clk@0030 {
compatible = "rockchip,rk3188-pll-clk";
reg = <0x0030 0x10>;
mode-reg = <0x0040 12>;
status-reg = <0x00ac 8>;
clocks = <&xin24m>;
clock-output-names = "clk_gpll";
rockchip,pll-type = <CLK_PLL_3188>;
#clock-cells = <0>;
#clock-init-cells = <1>;
};
};
/* Select control regs */
clk_sel_cons {
compatible = "rockchip,rk-sel-cons";
#address-cells = <1>;
#size-cells = <1>;
ranges;
clk_sel_con0: sel-con@0044 {
compatible = "rockchip,rk3188-selcon";
reg = <0x0044 0x4>;
#address-cells = <1>;
#size-cells = <1>;
aclk_cpu_div: aclk_cpu_div {
compatible = "rockchip,rk3188-div-con";
rockchip,bits = <0 5>;
clocks = <&aclk_cpu>;
clock-output-names = "aclk_cpu";
#clock-cells = <0>;
rockchip,div-type = <CLK_DIVIDER_PLUS_ONE>;
rockchip,clkops-idx =
<CLKOPS_RATE_MUX_DIV>;
rockchip,flags = <CLK_SET_RATE_NO_REPARENT>;
};
aclk_cpu: aclk_cpu_mux {
compatible = "rockchip,rk3188-mux-con";
rockchip,bits = <5 1>;
clocks = <&clk_apll>, <&clk_gpll>;
clock-output-names = "aclk_cpu";
#clock-cells = <0>;
#clock-init-cells = <1>;
};
clk_core_peri: clk_core_peri_div {
compatible = "rockchip,rk3188-div-con";
rockchip,bits = <6 2>;
clocks = <&clk_core>;
clock-output-names = "clk_core_peri";
rockchip,div-type = <CLK_DIVIDER_USER_DEFINE>;
rockchip,clkops-idx = <CLKOPS_RATE_CORE_CHILD>;
#clock-cells = <0>;
rockchip,div-relations = <0x0 2
0x1 4
0x2 8
0x3 16>;
};
clk_core: clk_core_mux {
compatible = "rockchip,rk3188-mux-con";
rockchip,bits = <8 1>;
clocks = <&clk_apll>,
<&clk_gates0 1>;
clock-output-names = "clk_core";
rockchip,flags = <(CLK_GET_RATE_NOCACHE |
CLK_SET_RATE_NO_REPARENT)>;
#clock-cells = <0>;
#clock-init-cells = <1>;
};
clk_core_div: clk_core_div {
compatible = "rockchip,rk3188-div-con";
rockchip,bits = <9 5>;
clocks = <&clk_core>;
clock-output-names = "clk_core";
rockchip,div-type = <CLK_DIVIDER_PLUS_ONE>;
rockchip,clkops-idx = <CLKOPS_RATE_CORE>;
#clock-cells = <0>;
};
/* reg[15:14]: reserved */
};
clk_sel_con1: sel-con@0048 {
compatible = "rockchip,rk3188-selcon";
reg = <0x0048 0x4>;
#address-cells = <1>;
#size-cells = <1>;
/* reg[2:0]: reserved */
aclk_core: aclk_core_div {
compatible = "rockchip,rk3188-div-con";
rockchip,bits = <3 3>;
clocks = <&clk_core>;
clock-output-names = "aclk_core";
#clock-cells = <0>;
rockchip,div-type = <CLK_DIVIDER_USER_DEFINE>;
rockchip,clkops-idx = <CLKOPS_RATE_CORE_CHILD>;
rockchip,div-relations = <0x0 1
0x1 2
0x2 3
0x3 4
0x4 8>;
};
/* reg[7:6]: reserved */
hclk_cpu: hclk_cpu_div {
compatible = "rockchip,rk3188-div-con";
rockchip,bits = <8 2>;
clocks = <&aclk_cpu>;
rockchip,div-type = <CLK_DIVIDER_POWER_OF_TWO>;
clock-output-names = "hclk_cpu";
#clock-cells = <0>;
#clock-init-cells = <1>;
};
/* reg[11:10]: reserved */
pclk_cpu: pclk_cpu_div {
compatible = "rockchip,rk3188-div-con";
rockchip,bits = <12 2>;
clocks = <&aclk_cpu>;
rockchip,div-type = <CLK_DIVIDER_POWER_OF_TWO>;
clock-output-names = "pclk_cpu";
#clock-cells = <0>;
#clock-init-cells = <1>;
};
pclk_ahb2apb: pclk_ahb2apb_div {
compatible = "rockchip,rk3188-div-con";
rockchip,bits = <14 2>;
clocks = <&hclk_cpu>;
rockchip,div-type = <CLK_DIVIDER_POWER_OF_TWO>;
clock-output-names = "pclk_ahb2apb";
#clock-cells = <0>;
#clock-init-cells = <1>;
};
};
clk_sel_con2: sel-con@004c {
compatible = "rockchip,rk3188-selcon";
reg = <0x004c 0x4>;
#address-cells = <1>;
#size-cells = <1>;
/* reg[14:0]: reserved */
clk_i2s_pll_mux: clk_i2s_pll_mux {
compatible = "rockchip,rk3188-mux-con";
rockchip,bits = <15 1>;
clocks = <&clk_gpll>, <&clk_cpll>;
clock-output-names = "clk_i2s_pll";
#clock-cells = <0>;
#clock-init-cells = <1>;
};
};
clk_sel_con3: sel-con@0050 {
compatible = "rockchip,rk3188-selcon";
reg = <0x0050 0x4>;
#address-cells = <1>;
#size-cells = <1>;
clk_i2s_div: clk_i2s_div {
compatible = "rockchip,rk3188-div-con";
rockchip,bits = <0 7>;
clocks = <&clk_i2s_pll_mux>;
rockchip,div-type = <CLK_DIVIDER_PLUS_ONE>;
clock-output-names = "clk_i2s_div";
#clock-cells = <0>;
};
/* reg[7]: reserved */
clk_i2s: clk_i2s_mux {
compatible = "rockchip,rk3188-mux-con";
rockchip,bits = <8 2>;
clocks = <&clk_i2s_div>, <&clk_i2s_frac>, <&xin12m>;
clock-output-names = "clk_i2s";
rockchip,clkops-idx = <CLKOPS_RATE_I2S>;
rockchip,flags = <CLK_SET_RATE_PARENT>;
#clock-cells = <0>;
};
/* reg[15:10]: reserved */
};
/* clk_sel_con4: reserved */
clk_sel_con5: sel-con@0058 {
compatible = "rockchip,rk3188-selcon";
reg = <0x0058 0x4>;
#address-cells = <1>;
#size-cells = <1>;
clk_spdif_div: clk_spdif_div {
compatible = "rockchip,rk3188-div-con";
rockchip,bits = <0 7>;
clocks = <&clk_i2s_pll_mux>;
rockchip,div-type = <CLK_DIVIDER_PLUS_ONE>;
clock-output-names = "clk_spdif_div";
/* spdif same as i2s */
#clock-cells = <0>;
};
/* reg[7]: reserved */
clk_spdif: clk_spdif_mux {
compatible = "rockchip,rk3188-mux-con";
rockchip,bits = <8 2>;
clocks = <&clk_spdif_div>, <&clk_spdif_frac>, <&xin12m>;
clock-output-names = "clk_spdif";
rockchip,clkops-idx = <CLKOPS_RATE_I2S>;
rockchip,flags = <CLK_SET_RATE_PARENT>;
#clock-cells = <0>;
};
/* reg[15:10]: reserved */
};
/* clk_sel_con6: reserved */
clk_sel_con7: sel-con@0060 {
compatible = "rockchip,rk3188-selcon";
reg = <0x0060 0x4>;
#address-cells = <1>;
#size-cells = <1>;
clk_i2s_frac: clk_i2s_frac {
compatible = "rockchip,rk3188-frac-con";
clocks = <&clk_i2s_div>;
clock-output-names = "clk_i2s_frac";
/* numerator denominator */
rockchip,bits = <0 32>;
#clock-cells = <0>;
rockchip,clkops-idx =
<CLKOPS_RATE_I2S_FRAC>;
};
};
/* clk_sel_con8: reserved */
clk_sel_con9: sel-con@0068 {
compatible = "rockchip,rk3188-selcon";
reg = <0x0068 0x4>;
#address-cells = <1>;
#size-cells = <1>;
clk_spdif_frac: clk_spdif_frac {
compatible = "rockchip,rk3188-frac-con";
clocks = <&clk_spdif_div>;
clock-output-names = "clk_spdif_frac";
/* numerator denominator */
rockchip,bits = <0 32>;
#clock-cells = <0>;
rockchip,clkops-idx =
<CLKOPS_RATE_I2S_FRAC>;
};
};
clk_sel_con10: sel-con@006c {
compatible = "rockchip,rk3188-selcon";
reg = <0x006c 0x4>;
#address-cells = <1>;
#size-cells = <1>;
aclk_peri_div: aclk_peri_div {
compatible = "rockchip,rk3188-div-con";
rockchip,bits = <0 5>;
clocks = <&aclk_peri>;
clock-output-names = "aclk_peri";
rockchip,div-type = <CLK_DIVIDER_PLUS_ONE>;
#clock-cells = <0>;
#clock-init-cells = <1>;
rockchip,clkops-idx =
<CLKOPS_RATE_MUX_DIV>;
rockchip,flags = <CLK_SET_RATE_NO_REPARENT>;
};
/* reg[7:5]: reserved */
hclk_peri: hclk_peri_div {
compatible = "rockchip,rk3188-div-con";
rockchip,bits = <8 2>;
clocks = <&aclk_peri>;
clock-output-names = "hclk_peri";
rockchip,div-type = <CLK_DIVIDER_POWER_OF_TWO>;
#clock-cells = <0>;
#clock-init-cells = <1>;
};
/* reg[11:10]: reserved */
pclk_peri: pclk_peri_div {
compatible = "rockchip,rk3188-div-con";
rockchip,bits = <12 2>;
clocks = <&aclk_peri>;
clock-output-names = "pclk_peri";
rockchip,div-type = <CLK_DIVIDER_POWER_OF_TWO>;
#clock-cells = <0>;
#clock-init-cells = <1>;
};
/* reg[14]: reserved */
aclk_peri: aclk_peri_mux {
compatible = "rockchip,rk3188-mux-con";
rockchip,bits = <15 1>;
clocks = <&clk_cpll>, <&clk_gpll>;
clock-output-names = "aclk_peri";
#clock-cells = <0>;
#clock-init-cells = <1>;
};
};
clk_sel_con11: sel-con@0070 {
compatible = "rockchip,rk3188-selcon";
reg = <0x0070 0x4>;
#address-cells = <1>;
#size-cells = <1>;
clk_sdmmc: clk_sdmmc_div {
compatible = "rockchip,rk3188-div-con";
rockchip,bits = <0 6>;
clocks = <&hclk_peri>;
clock-output-names = "clk_sdmmc";
rockchip,div-type = <CLK_DIVIDER_PLUS_ONE>;
rockchip,clkops-idx =
<CLKOPS_RATE_EVENDIV>;
#clock-cells = <0>;
};
/* reg[7:6]: reserved */
clk_ehci1phy12m: ehci1_phy_div {
compatible = "rockchip,rk3188-div-con";
rockchip,bits = <8 6>;
clocks = <&clk_ehci1phy480m>;
clock-output-names = "clk_ehci1phy12m";
rockchip,div-type = <CLK_DIVIDER_PLUS_ONE>;
#clock-cells = <0>;
};
/* reg[15:14]: reserved */
};
clk_sel_con12: sel-con@0074 {
compatible = "rockchip,rk3188-selcon";
reg = <0x0074 0x4>;
#address-cells = <1>;
#size-cells = <1>;
clk_sdio: clk_sdio_div {
compatible = "rockchip,rk3188-div-con";
rockchip,bits = <0 6>;
clocks = <&hclk_peri>;
clock-output-names = "clk_sdio";
rockchip,div-type = <CLK_DIVIDER_PLUS_ONE>;
rockchip,clkops-idx =
<CLKOPS_RATE_EVENDIV>;
#clock-cells = <0>;
};
/* reg[7:6]: reserved */
clk_emmc: clk_emmc_div {
compatible = "rockchip,rk3188-div-con";
rockchip,bits = <8 6>;
clocks = <&hclk_peri>;
clock-output-names = "clk_emmc";
rockchip,div-type = <CLK_DIVIDER_PLUS_ONE>;
rockchip,clkops-idx =
<CLKOPS_RATE_EVENDIV>;
#clock-cells = <0>;
};
/* reg[14]: reserved */
clk_uart_pll_mux: clk_uart_pll_mux {
compatible = "rockchip,rk3188-mux-con";
rockchip,bits = <15 1>;
clocks = <&clk_gpll>, <&clk_cpll>;
clock-output-names = "clk_uart_pll";
#clock-cells = <0>;
#clock-init-cells = <1>;
};
};
clk_sel_con13: sel-con@0078 {
compatible = "rockchip,rk3188-selcon";
reg = <0x0078 0x4>;
#address-cells = <1>;
#size-cells = <1>;
clk_uart0_div: clk_uart0_div {
compatible = "rockchip,rk3188-div-con";
rockchip,bits = <0 7>;
clocks = <&clk_uart_pll_mux>;
clock-output-names = "clk_uart0_div";
rockchip,div-type = <CLK_DIVIDER_PLUS_ONE>;
#clock-cells = <0>;
};
/* reg[7]: reserved */
clk_uart0: clk_uart0_mux {
compatible = "rockchip,rk3188-mux-con";
rockchip,bits = <8 2>;
clocks = <&clk_uart0_div>, <&clk_uart0_frac>,
<&xin24m>;
rockchip,clkops-idx =
<CLKOPS_RATE_UART>;
rockchip,flags = <CLK_SET_RATE_PARENT>;
clock-output-names = "clk_uart0";
#clock-cells = <0>;
};
/* reg[15:10]: reserved */
};
clk_sel_con14: sel-con@007c {
compatible = "rockchip,rk3188-selcon";
reg = <0x007c 0x4>;
#address-cells = <1>;
#size-cells = <1>;
clk_uart1_div: clk_uart1_div {
compatible = "rockchip,rk3188-div-con";
rockchip,bits = <0 7>;
clocks = <&clk_uart_pll_mux>;
clock-output-names = "clk_uart1_div";
rockchip,div-type = <CLK_DIVIDER_PLUS_ONE>;
#clock-cells = <0>;
};
/* reg[7]: reserved */
clk_uart1: clk_uart1_mux {
compatible = "rockchip,rk3188-mux-con";
rockchip,bits = <8 2>;
clocks = <&clk_uart1_div>, <&clk_uart1_frac>,
<&xin24m>;
rockchip,clkops-idx =
<CLKOPS_RATE_UART>;
rockchip,flags = <CLK_SET_RATE_PARENT>;
clock-output-names = "clk_uart1";
#clock-cells = <0>;
};
/* reg[15:10]: reserved */
};
clk_sel_con15: sel-con@0080 {
compatible = "rockchip,rk3188-selcon";
reg = <0x0080 0x4>;
#address-cells = <1>;
#size-cells = <1>;
clk_uart2_div: clk_uart2_div {
compatible = "rockchip,rk3188-div-con";
rockchip,bits = <0 7>;
clocks = <&clk_uart_pll_mux>;
clock-output-names = "clk_uart2_div";
rockchip,div-type = <CLK_DIVIDER_PLUS_ONE>;
#clock-cells = <0>;
};
/* reg[7]: reserved */
clk_uart2: clk_uart2_mux {
compatible = "rockchip,rk3188-mux-con";
rockchip,bits = <8 2>;
clocks = <&clk_uart2_div>, <&clk_uart2_frac>,
<&xin24m>;
rockchip,clkops-idx =
<CLKOPS_RATE_UART>;
rockchip,flags = <CLK_SET_RATE_PARENT>;
clock-output-names = "clk_uart2";
#clock-cells = <0>;
};
/* reg[15:10]: reserved */
};
clk_sel_con16: sel-con@0084 {
compatible = "rockchip,rk3188-selcon";
reg = <0x0084 0x4>;
#address-cells = <1>;
#size-cells = <1>;
clk_uart3_div: clk_uart3_div {
compatible = "rockchip,rk3188-div-con";
rockchip,bits = <0 7>;
clocks = <&clk_uart_pll_mux>;
clock-output-names = "clk_uart3_div";
rockchip,div-type = <CLK_DIVIDER_PLUS_ONE>;
#clock-cells = <0>;
};
/* reg[7]: reserved */
clk_uart3: clk_uart3_mux {
compatible = "rockchip,rk3188-mux-con";
rockchip,bits = <8 2>;
clocks = <&clk_uart3_div>, <&clk_uart3_frac>,
<&xin24m>;
rockchip,clkops-idx =
<CLKOPS_RATE_UART>;
rockchip,flags = <CLK_SET_RATE_PARENT>;
clock-output-names = "clk_uart3";
#clock-cells = <0>;
};
/* reg[15:10]: reserved */
};
clk_sel_con17: sel-con@0088 {
compatible = "rockchip,rk3188-selcon";
reg = <0x0088 0x4>;
#address-cells = <1>;
#size-cells = <1>;
clk_uart0_frac: clk_uart0_frac {
compatible = "rockchip,rk3188-frac-con";
clocks = <&clk_uart0_div>;
clock-output-names = "clk_uart0_frac";
/* numerator denominator */
rockchip,bits = <0 32>;
rockchip,clkops-idx =
<CLKOPS_RATE_FRAC>;
#clock-cells = <0>;
};
};
clk_sel_con18: sel-con@008c {
compatible = "rockchip,rk3188-selcon";
reg = <0x008c 0x4>;
#address-cells = <1>;
#size-cells = <1>;
clk_uart1_frac: clk_uart1_frac {
compatible = "rockchip,rk3188-frac-con";
clocks = <&clk_uart1_div>;
clock-output-names = "clk_uart1_frac";
/* numerator denominator */
rockchip,bits = <0 32>;
rockchip,clkops-idx =
<CLKOPS_RATE_FRAC>;
#clock-cells = <0>;
};
};
clk_sel_con19: sel-con@0090 {
compatible = "rockchip,rk3188-selcon";
reg = <0x0090 0x4>;
#address-cells = <1>;
#size-cells = <1>;
clk_uart2_frac: clk_uart2_frac {
compatible = "rockchip,rk3188-frac-con";
clocks = <&clk_uart2_div>;
clock-output-names = "clk_uart2_frac";
/* numerator denominator */
rockchip,bits = <0 32>;
rockchip,clkops-idx =
<CLKOPS_RATE_FRAC>;
#clock-cells = <0>;
};
};
clk_sel_con20: sel-con@0094 {
compatible = "rockchip,rk3188-selcon";
reg = <0x0094 0x4>;
#address-cells = <1>;
#size-cells = <1>;
clk_uart3_frac: clk_uart3_frac {
compatible = "rockchip,rk3188-frac-con";
clocks = <&clk_uart3_div>;
clock-output-names = "clk_uart3_frac";
/* numerator denominator */
rockchip,bits = <0 32>;
rockchip,clkops-idx =
<CLKOPS_RATE_FRAC>;
#clock-cells = <0>;
};
};
clk_sel_con21: sel-con@0098 {
compatible = "rockchip,rk3188-selcon";
reg = <0x0098 0x4>;
#address-cells = <1>;
#size-cells = <1>;
clk_mac_pll_mux: clk_mac_pll_mux {
compatible = "rockchip,rk3188-mux-con";
rockchip,bits = <0 1>;
clocks = <&clk_gpll>, <&clk_dpll>;
clock-output-names = "clk_mac_pll";
#clock-cells = <0>;
};
/* reg[3:1]: reserved */
clk_mac: clk_mac_mux {
compatible = "rockchip,rk3188-mux-con";
rockchip,bits = <4 1>;
clocks = <&clk_mac_pll_mux>, <&rmii_clkin>;
rockchip,clkops-idx =
<CLKOPS_RATE_MAC_REF>;
rockchip,flags = <CLK_SET_RATE_PARENT>;
clock-output-names = "clk_mac";
#clock-cells = <0>;
};
/* reg[7:5]: reserved */
clk_mac_pll_div: clk_mac_pll_div {
compatible = "rockchip,rk3188-div-con";
rockchip,bits = <8 5>;
clocks = <&clk_mac_pll_mux>;
clock-output-names = "clk_mac_pll";
rockchip,clkops-idx =
<CLKOPS_RATE_MUX_DIV>;
rockchip,div-type = <CLK_DIVIDER_PLUS_ONE>;
#clock-cells = <0>;
};
/* reg[15:13]: reserved */
};
clk_sel_con22: sel-con@009c {
compatible = "rockchip,rk3188-selcon";
reg = <0x009c 0x4>;
#address-cells = <1>;
#size-cells = <1>;
clk_hsadc_pll_mux: clk_hsadc_pll_mux {
compatible = "rockchip,rk3188-mux-con";
rockchip,bits = <0 1>;
clocks = <&clk_gpll>, <&clk_cpll>;
clock-output-names = "clk_hsadc_pll";
#clock-cells = <0>;
};
/* reg[3:1]: reserved */
clk_hsadc: clk_hsadc_mux {
compatible = "rockchip,rk3188-mux-con";
rockchip,bits = <4 2>;
clocks = <&clk_hsadc_pll_mux>, <&clk_hsadc_frac>,
<&clk_hsadc_ext>;
rockchip,clkops-idx =
<CLKOPS_RATE_HSADC>;
rockchip,flags = <CLK_SET_RATE_PARENT>;
clock-output-names = "clk_hsadc";
#clock-cells = <0>;
};
/* reg[6]: reserved */
clk_hsadc_inv: clk_hsadc_inv {
compatible = "rockchip,rk3188-inv-con";
rockchip,bits = <7 1>;
clocks = <&clk_hsadc>;
};
clk_hsadc_div: clk_hsadc_div {
compatible = "rockchip,rk3188-div-con";
rockchip,bits = <8 8>;
clocks = <&clk_hsadc_pll_mux>;
clock-output-names = "clk_hsadc_pll";
rockchip,div-type = <CLK_DIVIDER_PLUS_ONE>;
#clock-cells = <0>;
};
};
clk_sel_con23: sel-con@00a0 {
compatible = "rockchip,rk3188-selcon";
reg = <0x00a0 0x4>;
#address-cells = <1>;
#size-cells = <1>;
clk_hsadc_frac: clk_hsadc_frac{
compatible = "rockchip,rk3188-frac-con";
clocks = <&clk_hsadc_pll_mux>;
clock-output-names = "clk_hsadc_frac";
/* numerator denominator */
rockchip,bits = <0 32>;
rockchip,clkops-idx =
<CLKOPS_RATE_FRAC>;
#clock-cells = <0>;
};
};
clk_sel_con24: sel-con@00a4 {
compatible = "rockchip,rk3188-selcon";
reg = <0x00a4 0x4>;
#address-cells = <1>;
#size-cells = <1>;
clk_saradc: clk_saradc_div {
compatible = "rockchip,rk3188-div-con";
rockchip,bits = <8 8>;
clocks = <&xin24m>;
clock-output-names = "clk_saradc";
rockchip,div-type = <CLK_DIVIDER_PLUS_ONE>;
#clock-cells = <0>;
};
};
clk_sel_con25: sel-con@00a8 {
compatible = "rockchip,rk3188-selcon";
reg = <0x00a8 0x4>;
#address-cells = <1>;
#size-cells = <1>;
clk_spi0: clk_spi0_div {
compatible = "rockchip,rk3188-div-con";
rockchip,bits = <0 7>;
clocks = <&pclk_peri>;
clock-output-names = "clk_spi0";
rockchip,div-type = <CLK_DIVIDER_PLUS_ONE>;
#clock-cells = <0>;
};
/* reg[7]: reserved */
clk_spi1: clk_spi1_div {
compatible = "rockchip,rk3188-div-con";
rockchip,bits = <8 7>;
clocks = <&pclk_peri>;
clock-output-names = "clk_spi1";
rockchip,div-type = <CLK_DIVIDER_PLUS_ONE>;
#clock-cells = <0>;
};
/* reg[15]: reserved */
};
clk_sel_con26: sel-con@00ac {
compatible = "rockchip,rk3188-selcon";
reg = <0x00ac 0x4>;
#address-cells = <1>;
#size-cells = <1>;
clk_ddr_div: clk_ddr_div {
compatible = "rockchip,rk3188-div-con";
rockchip,bits = <0 2>;
clocks = <&clk_ddr>;
clock-output-names = "clk_ddr";
rockchip,div-type = <CLK_DIVIDER_POWER_OF_TWO>;
rockchip,clkops-idx = <CLKOPS_RATE_DDR>;
#clock-cells = <0>;
};
/* reg[7:2]: reserved */
clk_ddr: clk_ddr_mux {
compatible = "rockchip,rk3188-mux-con";
rockchip,bits = <8 1>;
clocks = <&clk_dpll>,
<&clk_gates1 7>;
clock-output-names = "clk_ddr";
rockchip,flags = <(CLK_GET_RATE_NOCACHE |
CLK_SET_RATE_NO_REPARENT)>;
#clock-cells = <0>;
};
/* reg[15:9]: reserved */
};
clk_sel_con27: sel-con@00b0 {
compatible = "rockchip,rk3188-selcon";
reg = <0x00b0 0x4>;
#address-cells = <1>;
#size-cells = <1>;
dclk_lcdc0: dclk_lcdc0_mux {
compatible = "rockchip,rk3188-mux-con";
rockchip,bits = <0 1>;
clocks = <&clk_cpll>, <&clk_gpll>;
clock-output-names = "dclk_lcdc0";
#clock-cells = <0>;
};
/* reg[7:1]: reserved */
dclk_lcdc0_div: dclk_lcdc0_div {
compatible = "rockchip,rk3188-div-con";
rockchip,bits = <8 8>;
clocks = <&dclk_lcdc0>;
clock-output-names = "dclk_lcdc0";
rockchip,div-type = <CLK_DIVIDER_PLUS_ONE>;
rockchip,clkops-idx =
<CLKOPS_RATE_MUX_EVENDIV>;
#clock-cells = <0>;
};
};
clk_sel_con28: sel-con@00b4 {
compatible = "rockchip,rk3188-selcon";
reg = <0x00b4 0x4>;
#address-cells = <1>;
#size-cells = <1>;
dclk_lcdc1: dclk_lcdc1_mux {
compatible = "rockchip,rk3188-mux-con";
rockchip,bits = <0 1>;
clocks = <&clk_cpll>, <&clk_gpll>;
clock-output-names = "dclk_lcdc1";
#clock-cells = <0>;
};
/* reg[7:1]: reserved */
dclk_lcdc1_div: dclk_lcdc1_div {
compatible = "rockchip,rk3188-div-con";
rockchip,bits = <8 8>;
clocks = <&dclk_lcdc1>;
clock-output-names = "dclk_lcdc1";
rockchip,div-type = <CLK_DIVIDER_PLUS_ONE>;
rockchip,clkops-idx =
<CLKOPS_RATE_MUX_EVENDIV>;
#clock-cells = <0>;
};
};
clk_sel_con29: sel-con@00b8 {
compatible = "rockchip,rk3188-selcon";
reg = <0x00b8 0x4>;
#address-cells = <1>;
#size-cells = <1>;
cif_out_pll_mux: cif_out_pll_mux {
compatible = "rockchip,rk3188-mux-con";
rockchip,bits = <0 1>;
clocks = <&clk_cpll>, <&clk_gpll>;
clock-output-names = "cif_out_pll";
#clock-cells = <0>;
};
cif0_out_div: cif0_out_div {
compatible = "rockchip,rk3188-div-con";
rockchip,bits = <1 5>;
clocks = <&cif_out_pll_mux>;
clock-output-names = "cif_out_pll";
rockchip,div-type = <CLK_DIVIDER_PLUS_ONE>;
rockchip,clkops-idx =
<CLKOPS_RATE_MUX_DIV>;
#clock-cells = <0>;
};
/* reg[6]: reserved */
clk_cif0: cif0_out_mux {
compatible = "rockchip,rk3188-mux-con";
rockchip,bits = <7 1>;
clocks = <&cif_out_pll_mux>, <&xin24m>;
rockchip,clkops-idx =
<CLKOPS_RATE_CIFOUT>;
rockchip,flags = <CLK_SET_RATE_PARENT>;
clock-output-names = "clk_cif0";
#clock-cells = <0>;
};
/* reg[15:8]: reserved */
};
clk_sel_con30: sel-con@00bc {
compatible = "rockchip,rk3188-selcon";
reg = <0x00bc 0x4>;
#address-cells = <1>;
#size-cells = <1>;
clk_ehci1phy480m: clk_ehci1phy480m_mux {
compatible = "rockchip,rk3188-mux-con";
rockchip,bits = <0 2>;
clocks = <&otgphy0_480m>, <&otgphy1_480m>,
<&clk_gpll>, <&clk_cpll>;
clock-output-names = "clk_ehci1phy480m";
#clock-cells = <0>;
};
/* reg[7:2]: reserved */
/* inv here?????? */
/* reg[15:9]: reserved */
};
clk_sel_con31: sel-con@00c0 {
compatible = "rockchip,rk3188-selcon";
reg = <0x00c0 0x4>;
#address-cells = <1>;
#size-cells = <1>;
aclk_lcdc0_pre_div: aclk_lcdc0_pre_div {
compatible = "rockchip,rk3188-div-con";
rockchip,bits = <0 5>;
clocks = <&aclk_lcdc0>;
clock-output-names = "aclk_lcdc0";
rockchip,div-type = <CLK_DIVIDER_PLUS_ONE>;
rockchip,clkops-idx =
<CLKOPS_RATE_MUX_DIV>;
#clock-cells = <0>;
};
/* reg[6:5]: reserved */
aclk_lcdc0: aclk_lcdc0_pre_mux {
compatible = "rockchip,rk3188-mux-con";
rockchip,bits = <7 1>;
clocks = <&clk_cpll>, <&clk_gpll>;
clock-output-names = "aclk_lcdc0";
#clock-cells = <0>;
#clock-init-cells = <1>;
};
aclk_lcdc1_pre_div: aclk_lcdc1_pre_div {
compatible = "rockchip,rk3188-div-con";
rockchip,bits = <8 5>;
clocks = <&aclk_lcdc1>;
clock-output-names = "aclk_lcdc1";
rockchip,div-type = <CLK_DIVIDER_PLUS_ONE>;
rockchip,clkops-idx =
<CLKOPS_RATE_MUX_DIV>;
#clock-cells = <0>;
};
/* reg[14:13]: reserved */
aclk_lcdc1: aclk_lcdc1_pre_mux {
compatible = "rockchip,rk3188-mux-con";
rockchip,bits = <15 1>;
clocks = <&clk_cpll>, <&clk_gpll>;
clock-output-names = "aclk_lcdc1";
#clock-cells = <0>;
#clock-init-cells = <1>;
};
};
clk_sel_con32: sel-con@00c4 {
compatible = "rockchip,rk3188-selcon";
reg = <0x00c4 0x4>;
#address-cells = <1>;
#size-cells = <1>;
aclk_vepu_div: aclk_vepu_div {
compatible = "rockchip,rk3188-div-con";
rockchip,bits = <0 5>;
clocks = <&clk_vepu>;
clock-output-names = "clk_vepu";
rockchip,div-type = <CLK_DIVIDER_PLUS_ONE>;
rockchip,clkops-idx =
<CLKOPS_RATE_MUX_DIV>;
#clock-cells = <0>;
};
/* reg[6:5]: reserved */
clk_vepu: aclk_vepu_mux {
compatible = "rockchip,rk3188-mux-con";
rockchip,bits = <7 1>;
clocks = <&clk_cpll>, <&clk_gpll>;
clock-output-names = "clk_vepu";
#clock-cells = <0>;
};
aclk_vdpu_div: aclk_vdpu_div {
compatible = "rockchip,rk3188-div-con";
rockchip,bits = <8 5>;
clocks = <&clk_vdpu>;
clock-output-names = "clk_vdpu";
rockchip,div-type = <CLK_DIVIDER_PLUS_ONE>;
rockchip,clkops-idx =
<CLKOPS_RATE_MUX_DIV>;
#clock-cells = <0>;
};
/* reg[14:13]: reserved */
clk_vdpu: aclk_vdpu_mux {
compatible = "rockchip,rk3188-mux-con";
rockchip,bits = <15 1>;
clocks = <&clk_cpll>, <&clk_gpll>;
clock-output-names = "clk_vdpu";
#clock-cells = <0>;
};
};
clk_sel_con34: sel-con@00cc {
compatible = "rockchip,rk3188-selcon";
reg = <0x00cc 0x4>;
#address-cells = <1>;
#size-cells = <1>;
aclk_gpu_div: aclk_gpu_div {
compatible = "rockchip,rk3188-div-con";
rockchip,bits = <0 5>;
clocks = <&clk_gpu>;
clock-output-names = "clk_gpu";
rockchip,div-type = <CLK_DIVIDER_PLUS_ONE>;
rockchip,clkops-idx =
<CLKOPS_RATE_MUX_DIV>;
#clock-cells = <0>;
};
/* reg[6:5]: reserved */
clk_gpu: aclk_gpu_mux {
compatible = "rockchip,rk3188-mux-con";
rockchip,bits = <7 1>;
clocks = <&clk_cpll>, <&clk_gpll>;
clock-output-names = "clk_gpu";
#clock-cells = <0>;
#clock-init-cells = <1>;
};
/* reg[15:8]: reserved */
};
};
/* Gate control regs */
clk_gate_cons {
compatible = "rockchip,rk-gate-cons";
#address-cells = <1>;
#size-cells = <1>;
ranges ;
clk_gates0: gate-clk@00d0 {
compatible = "rockchip,rk3188-gate-clk";
reg = <0x00d0 0x4>;
clocks = <&clk_core_peri>, <&clk_gpll>,
<&clk_dpll>, <&aclk_cpu>,
<&hclk_cpu>, <&pclk_cpu>,
<&pclk_cpu>, <&aclk_core>,
<&dummy>, <&clk_i2s_div>,
<&clk_i2s_frac>, <&dummy>,
<&dummy>, <&clk_spdif_div>,
<&clk_spdif_frac>, <&dummy>;
clock-output-names =
"clk_core_peri", "clk_arm_gpll",
"clk_dpll", "aclk_cpu",
"hclk_cpu", "pclk_cpu",
"g_atclk_cpu", "aclk_core",
"reserved", "clk_i2s_div",
"clk_i2s_frac", "reserved",
"reserved", "clk_spdif_div",
"clk_spdif_frac", "g_testclk";
rockchip,suspend-clkgating-setting=<0x00bf 0x00bf>;
#clock-cells = <1>;
};
clk_gates1: gate-clk@00d4 {
compatible = "rockchip,rk3188-gate-clk";
reg = <0x00d4 0x4>;
clocks = <&xin24m>, <&xin24m>,
<&xin24m>, <&dummy>,
<&aclk_lcdc1>, <&xin24m>,
<&xin24m>, <&clk_gpll>,
<&clk_uart0_div>, <&clk_uart0_frac>,
<&clk_uart1_div>, <&clk_uart1_frac>,
<&clk_uart2_div>, <&clk_uart2_frac>,
<&clk_uart3_div>, <&clk_uart3_frac>;
clock-output-names =
"timer0", "timer1",
"timer3", "g_jtag",
"aclk_lcdc1", "g_otgphy0",
"g_otgphy1", "clk_ddr_gpll",
"clk_uart0_div", "clk_uart0_frac",
"clk_uart1_div", "clk_uart1_frac",
"clk_uart2_div", "clk_uart2_frac",
"clk_uart3_div", "clk_uart3_frac";
rockchip,suspend-clkgating-setting=<0x0 0x0>;
#clock-cells = <1>;
};
clk_gates2: gate-clk@00d8 {
compatible = "rockchip,rk3188-gate-clk";
reg = <0x00d8 0x4>;
clocks = <&aclk_peri>, <&aclk_peri>,
<&hclk_peri>, <&pclk_peri>,
<&hclk_peri>, <&clk_mac_pll_mux>,
<&clk_hsadc_pll_mux>, <&clk_hsadc_frac>,
<&clk_saradc>, <&clk_spi0>,
<&clk_spi1>, <&clk_sdmmc>,
<&dummy>, <&clk_sdio>,
<&clk_emmc>, <&dummy>;
clock-output-names =
"aclk_peri", "g_aclk_peri",
"hclk_peri", "pclk_peri",
"g_smc_src", "clk_mac_pll",
"clk_hsadc_pll", "clk_hsadc_frac",
"clk_saradc", "clk_spi0",
"clk_spi1", "clk_sdmmc",
"g_mac_lbtest", "clk_sdio",
"clk_emmc", "reserved";
//rockchip,suspend-clkgating-setting=<0x1f 0x1b>;
rockchip,suspend-clkgating-setting=<0x1f 0x1b>;
#clock-cells = <1>;
};
clk_gates3: gate-clk@00dc {
compatible = "rockchip,rk3188-gate-clk";
reg = <0x00dc 0x4>;
clocks = <&aclk_lcdc0>, <&dclk_lcdc0>,
<&dclk_lcdc1>, <&clk_cif_in>,
<&xin24m>, <&xin24m>,
<&clk_ehci1phy480m>, <&clk_cif0>,
<&xin24m>, <&clk_vepu>,
<&clk_vepu>, <&clk_vdpu>,
<&clk_vdpu>, <&dummy>,
<&xin24m>, <&clk_gpu>;
clock-output-names =
"aclk_lcdc0", "dclk_lcdc0",
"dclk_lcdc1", "g_clk_cif_in",
/*
* FIXME: cif_out_pll can be set to
* clk_cif as virtual
*/
"timer2", "timer4",
"clk_ehci1phy480m", "clk_cif0",
"timer5", "clk_vepu",
"g_h_vepu", "clk_vdpu",
"g_h_vdpu", "reserved",
"timer6", "clk_gpu";
rockchip,suspend-clkgating-setting=<0x0 0x0>;
#clock-cells = <1>;
};
clk_gates4: gate-clk@00e0 {
compatible = "rockchip,rk3188-gate-clk";
reg = <0x00e0 0x4>;
clocks = <&hclk_peri>, <&pclk_peri>,
<&aclk_peri>, <&aclk_peri>,
<&aclk_peri>, <&hclk_peri>,
<&hclk_peri>, <&hclk_peri>,
<&hclk_cpu>, <&hclk_cpu>,
<&aclk_cpu>, <&dummy>,
<&aclk_cpu>, <&dummy>,
<&hclk_cpu>, <&hclk_cpu>;
/*
* g_ap: gate_aclk_peri_...
* g_hp: gate_hclk_peri_...
* g_pp: gate_pclk_peri_...
*/
clock-output-names =
"g_hp_axi_matrix", "g_pp_axi_matrix",
"g_a_cpu_peri", "g_ap_axi_matrix",
"g_a_peri_niu", "g_h_usb_peri",
"g_hp_ahb_arbi", "g_h_emem_peri",
"g_h_cpubus", "g_h_ahb2apb",
"g_a_strc_sys", "reserved",
"g_a_intmem", "reserved",
"g_h_imem1", "g_h_imem0";
//rockchip,suspend-clkgating-setting=<0xd75e 0xd75e>;
rockchip,suspend-clkgating-setting=<0xd75e 0xd75e>;
#clock-cells = <1>;
};
clk_gates5: gate-clk@00e4 {
compatible = "rockchip,rk3188-gate-clk";
reg = <0x00e4 0x4>;
clocks = <&aclk_cpu>, <&aclk_peri>,
<&pclk_cpu>, <&pclk_cpu>,
<&pclk_cpu>, <&pclk_cpu>,
<&hclk_cpu>, <&pclk_cpu>,
<&aclk_peri>, <&hclk_peri>,
<&hclk_peri>, <&hclk_peri>,
<&hclk_peri>, <&hclk_peri>;
clock-output-names =
"g_a_dmac1", "g_a_dmac2",
"g_p_efuse", "g_p_tzpc",
"g_p_grf", "g_p_pmu",
"g_h_rom", "g_p_ddrupctl",
"g_a_smc", "g_h_nandc",
"g_h_sdmmc0", "g_h_sdio",
"g_h_emmc", "g_h_otg0";
rockchip,suspend-clkgating-setting=<0x80 0x80>;
#clock-cells = <1>;
};
clk_gates6: gate-clk@00e8 {
compatible = "rockchip,rk3188-gate-clk";
reg = <0x00e8 0x4>;
clocks = <&clk_gates6 13>, <&hclk_cpu>,
<&hclk_cpu>, <&clk_gates9 5>,
<&hclk_cpu>, <&clk_gates6 13>,
<&dummy>, <&dummy>,
<&clk_gates6 13>, <&hclk_cpu>,
<&hclk_cpu>, <&clk_gates9 5>,
<&hclk_cpu>, <&aclk_lcdc0>;
clock-output-names =
"g_a_lcdc0", "g_h_lcdc0",
"g_h_lcdc1", "g_a_lcdc1",
"g_h_cif0", "g_a_cif0",
"reserved", "reserved",
"g_a_ipp", "g_h_ipp",
"g_h_rga", "g_a_rga",
"g_h_vio_bus", "g_a_vio0";
rockchip,suspend-clkgating-setting=<0x0 0x0>;
#clock-cells = <1>;
};
clk_gates7: gate-clk@00ec {
compatible = "rockchip,rk3188-gate-clk";
reg = <0x00ec 0x4>;
clocks = <&hclk_peri>, <&hclk_cpu>,
<&hclk_cpu>, <&hclk_peri>,
<&hclk_peri>, <&hclk_peri>,
<&hclk_peri>, <&pclk_cpu>,
<&dummy>, <&pclk_cpu>,
<&pclk_cpu>, <&pclk_peri>,
<&pclk_peri>, <&pclk_peri>,
<&pclk_peri>, <&pclk_peri>;
clock-output-names =
"g_h_emac", "g_h_spdif",
"g_h_i2s0_2ch", "g_h_otg1",
"g_h_ehci1", "g_h_hsadc",
"g_h_pidf", "g_p_timer0",
"reserved", "g_p_timer2",
"g_p_pwm01", "g_p_pwm23",
"g_p_spi0", "g_p_spi1",
"g_p_saradc", "g_p_wdt";
rockchip,suspend-clkgating-setting=<0x0 0x0>;
#clock-cells = <1>;
};
clk_gates8: gate-clk@00f0 {
compatible = "rockchip,rk3188-gate-clk";
reg = <0x00f0 0x4>;
clocks = <&pclk_ahb2apb>, <&pclk_ahb2apb>,
<&pclk_peri>, <&pclk_peri>,
<&pclk_cpu>, <&pclk_cpu>,
<&pclk_peri>, <&pclk_peri>,
<&pclk_peri>, <&pclk_cpu>,
<&pclk_cpu>, <&pclk_cpu>,
<&pclk_peri>, <&aclk_peri>;
clock-output-names =
"g_p_uart0", "g_p_uart1",
"g_p_uart2", "g_p_uart3",
"g_p_i2c0", "g_p_i2c1",
"g_p_i2c2", "g_p_i2c3",
"g_p_i2c4", "g_p_gpio0",
"g_p_gpio1", "g_p_gpio2",
"g_p_gpio3", "g_a_gps";
rockchip,suspend-clkgating-setting=<0x200 0x200>;
#clock-cells = <1>;
};
clk_gates9: gate-clk@00f4 {
compatible = "rockchip,rk3188-gate-clk";
reg = <0x00f4 0x4>;
clocks = <&clk_core>, <&pclk_cpu>,
<&clk_gates0 6>, <&clk_gates0 6>,
<&clk_core>, <&aclk_lcdc1>,
<&pclk_cpu>, <&clk_gpu>;
clock-output-names =
"g_clk_core_dbg", "g_p_dbg",
"g_clk_trace", "g_atclk",
"g_clk_l2c", "g_a_vio1",
"g_p_ddrpubl", "g_a_gpu";
rockchip,suspend-clkgating-setting=<0x50 0x50>;
#clock-cells = <1>;
};
};
};
};
};
&cru SRST_LCDC1_AHB>, <&cru SRST_LCDC1_DCLK>;
reset-names = "axi", "ahb", "dclk";
iommus = <&vopl_mmu>;
status = "disabled";
vopl_out: port {
#address-cells = <1>;
#size-cells = <0>;
vopl_out_hdmi: endpoint@0 {
reg = <0>;
remote-endpoint = <&hdmi_in_vopl>;
};
vopl_out_edp: endpoint@1 {
reg = <1>;
remote-endpoint = <&edp_in_vopl>;
};
vopl_out_dsi0: endpoint@2 {
reg = <2>;
remote-endpoint = <&dsi0_in_vopl>;
};
vopl_out_lvds: endpoint@3 {
reg = <3>;
remote-endpoint = <&lvds_in_vopl>;
};
vopl_out_dsi1: endpoint@4 {
reg = <4>;
remote-endpoint = <&dsi1_in_vopl>;
};
};
};
vopl_mmu: iommu@ff940300 {
compatible = "rockchip,iommu";
reg = <0x0 0xff940300 0x0 0x100>;
interrupts = <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>;
interrupt-names = "vopl_mmu";
clocks = <&cru ACLK_VOP1>, <&cru HCLK_VOP1>;
clock-names = "aclk", "hclk";
power-domains = <&power RK3288_PD_VIO>;
#iommu-cells = <0>;
status = "disabled";
};
cif: cif@ff950000 {
compatible = "rockchip,cif";
reg = <0x0 0xff950000 0x0 0x400>;
interrupts = <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&cru ACLK_VIP>, <&cru HCLK_VIP>,
<&cru PCLK_VIP_IN>, <&cru SCLK_VIP_OUT>;
clock-names = "aclk_cif0", "hclk_cif0",
"cif0_in", "cif0_out";
resets = <&cru SRST_VIP>;
reset-names = "rst_cif";
pinctrl-names = "cif_pin_all";
pinctrl-0 = <&isp_mipi &isp_dvp_d2d9 &isp_dvp_d10d11>;
rockchip,grf = <&grf>;
rockchip,cru = <&cru>;
power-domains = <&power RK3288_PD_VIO>;
status = "disabled";
};
dsi0: dsi@ff960000 {
compatible = "rockchip,rk3288-mipi-dsi", "snps,dw-mipi-dsi";
reg = <0x0 0xff960000 0x0 0x4000>;
interrupts = <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&cru SCLK_MIPIDSI_24M>, <&cru PCLK_MIPI_DSI0>;
clock-names = "ref", "pclk";
resets = <&cru SRST_MIPIDSI0>;
reset-names = "apb";
power-domains = <&power RK3288_PD_VIO>;
rockchip,grf = <&grf>;
#address-cells = <1>;
#size-cells = <0>;
status = "disabled";
ports {
#address-cells = <1>;
#size-cells = <0>;
dsi0_in: port {
#address-cells = <1>;
#size-cells = <0>;
dsi0_in_vopb: endpoint@0 {
reg = <0>;
remote-endpoint = <&vopb_out_dsi0>;
};
dsi0_in_vopl: endpoint@1 {
reg = <1>;
remote-endpoint = <&vopl_out_dsi0>;
};
};
};
};
dsi1: dsi@ff964000 {
compatible = "rockchip,rk3288-mipi-dsi", "snps,dw-mipi-dsi";
reg = <0x0 0xff964000 0x0 0x4000>;
interrupts = <GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&cru SCLK_MIPIDSI_24M>, <&cru PCLK_MIPI_DSI1>;
clock-names = "ref", "pclk";
resets = <&cru SRST_MIPIDSI1>;
reset-names = "apb";
power-domains = <&power RK3288_PD_VIO>;
rockchip,grf = <&grf>;
#address-cells = <1>;
#size-cells = <0>;
status = "disabled";
ports {
#address-cells = <1>;
#size-cells = <0>;
dsi1_in: port {
#address-cells = <1>;
#size-cells = <0>;
dsi1_in_vopb: endpoint@0 {
reg = <0>;
remote-endpoint = <&vopb_out_dsi1>;
};
dsi1_in_vopl: endpoint@1 {
reg = <1>;
remote-endpoint = <&vopl_out_dsi1>;
};
};
};
};
mipi_phy_tx1rx1: mipi-phy-tx1rx1@ff968000 {
compatible = "rockchip,rk3288-mipi-dphy";
reg = <0x0 0xff968000 0x0 0x4000>;
rockchip,grf = <&grf>;
clocks = <&cru SCLK_MIPIDSI_24M>, <&cru PCLK_MIPI_CSI>;
clock-names = "dphy-ref", "pclk";
status = "disabled";
};
edp: dp@ff970000 {
compatible = "rockchip,rk3288-dp";
reg = <0x0 0xff970000 0x0 0x4000>;
interrupts = <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&cru SCLK_EDP>, <&cru PCLK_EDP_CTRL>;
clock-names = "dp", "pclk";
power-domains = <&power RK3288_PD_VIO>;
phys = <&edp_phy>;
phy-names = "dp";
resets = <&cru SRST_EDP>;
reset-names = "dp";
rockchip,grf = <&grf>;
status = "disabled";
ports {
#address-cells = <1>;
#size-cells = <0>;
edp_in: port@0 {
reg = <0>;
#address-cells = <1>;
#size-cells = <0>;
edp_in_vopb: endpoint@0 {
reg = <0>;
remote-endpoint = <&vopb_out_edp>;
};
edp_in_vopl: endpoint@1 {
reg = <1>;
remote-endpoint = <&vopl_out_edp>;
};
};
};
};
lvds: lvds@ff96c000 {
compatible = "rockchip,rk3288-lvds";
reg = <0x0 0xff96c000 0x0 0x4000>;
clocks = <&cru PCLK_LVDS_PHY>;
clock-names = "pclk_lvds";
power-domains = <&power RK3288_PD_VIO>;
rockchip,grf = <&grf>;
status = "disabled";
ports {
#address-cells = <1>;
#size-cells = <0>;
lvds_in: port@0 {
reg = <0>;
#address-cells = <1>;
#size-cells = <0>;
lvds_in_vopb: endpoint@0 {
reg = <0>;
remote-endpoint = <&vopb_out_lvds>;
};
lvds_in_vopl: endpoint@1 {
reg = <1>;
remote-endpoint = <&vopl_out_lvds>;
};
};
};
};
hdmi: hdmi@ff980000 {
compatible = "rockchip,rk3288-dw-hdmi";
reg = <0x0 0xff980000 0x0 0x20000>;
reg-io-width = <4>;
rockchip,grf = <&grf>;
interrupts = <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&cru PCLK_HDMI_CTRL>, <&cru SCLK_HDMI_HDCP>;
clock-names = "iahb", "isfr";
pinctrl-names = "default", "sleep";
pinctrl-0 = <&hdmi_ddc>;
pinctrl-1 = <&hdmi_gpio>;
power-domains = <&power RK3288_PD_VIO>;
status = "disabled";
ports {
hdmi_in: port {
#address-cells = <1>;
#size-cells = <0>;
hdmi_in_vopb: endpoint@0 {
reg = <0>;
remote-endpoint = <&vopb_out_hdmi>;
};
hdmi_in_vopl: endpoint@1 {
reg = <1>;
remote-endpoint = <&vopl_out_hdmi>;
};
};
};
};
vpu: video-codec@ff9a0000 {
compatible = "rockchip,rk3288-vpu";
reg = <0x0 0xff9a0000 0x0 0x800>;
interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>;
interrupt-names = "vepu", "vdpu";
clocks = <&cru ACLK_VCODEC>, <&cru HCLK_VCODEC>;
clock-names = "aclk", "hclk";
power-domains = <&power RK3288_PD_VIDEO>;
iommus = <&vpu_mmu>;
assigned-clocks = <&cru ACLK_VCODEC>;
assigned-clock-rates = <400000000>;
status = "disabled";
};
vpu_service: vpu-service@ff9a0000 {
compatible = "rockchip,vpu_service";
reg = <0x0 0xff9a0000 0x0 0x800>;
interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>;
interrupt-names = "irq_enc", "irq_dec";
clocks = <&cru ACLK_VCODEC>, <&cru HCLK_VCODEC>;
clock-names = "aclk_vcodec", "hclk_vcodec";
power-domains = <&power RK3288_PD_VIDEO>;
rockchip,grf = <&grf>;
resets = <&cru SRST_VCODEC_AXI>, <&cru SRST_VCODEC_AHB>;
reset-names = "video_a", "video_h";
iommus = <&vpu_mmu>;
iommu_enabled = <1>;
status = "disabled";
/* 0 means ion, 1 means drm */
allocator = <1>;
};
vpu_mmu: iommu@ff9a0800 {
compatible = "rockchip,iommu";
reg = <0x0 0xff9a0800 0x0 0x100>;
interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>;
interrupt-names = "vpu_mmu";
clocks = <&cru ACLK_VCODEC>, <&cru HCLK_VCODEC>;
clock-names = "aclk", "hclk";
power-domains = <&power RK3288_PD_VIDEO>;
#iommu-cells = <0>;
};
hevc_service: hevc-service@ff9c0000 {
compatible = "rockchip,hevc_service";
reg = <0x0 0xff9c0000 0x0 0x400>;
interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>;
interrupt-names = "irq_dec";
clocks = <&cru ACLK_HEVC>, <&cru HCLK_HEVC>,
<&cru SCLK_HEVC_CORE>,
<&cru SCLK_HEVC_CABAC>;
clock-names = "aclk_vcodec", "hclk_vcodec", "clk_core",
"clk_cabac";
/*
* The 4K hevc would also work well with 500/125/300/300,
* no more err irq and reset request.
*/
assigned-clocks = <&cru ACLK_HEVC>, <&cru HCLK_HEVC>,
<&cru SCLK_HEVC_CORE>,
<&cru SCLK_HEVC_CABAC>;
assigned-clock-rates = <400000000>, <100000000>,
<300000000>, <300000000>;
resets = <&cru SRST_HEVC>;
reset-names = "video";
power-domains = <&power RK3288_PD_HEVC>;
rockchip,grf = <&grf>;
iommus = <&hevc_mmu>;
iommu_enabled = <1>;
status = "disabled";
/* 0 means ion, 1 means drm */
allocator = <1>;
};
hevc_mmu: iommu@ff9c0440 {
compatible = "rockchip,iommu";
reg = <0x0 0xff9c0440 0x0 0x40>, <0x0 0xff9c0480 0x0 0x40>;
interrupts = <GIC_SPI 111 IRQ_TYPE_LEVEL_HIGH>;
interrupt-names = "hevc_mmu";
clocks = <&cru ACLK_HEVC>, <&cru HCLK_HEVC>,
<&cru SCLK_HEVC_CORE>,
<&cru SCLK_HEVC_CABAC>;
clock-names = "aclk", "hclk", "clk_core",
"clk_cabac";
power-domains = <&power RK3288_PD_HEVC>;
#iommu-cells = <0>;
};
gpu: gpu@ffa30000 {
compatible = "arm,malit764",
"arm,malit76x",
"arm,malit7xx",
"arm,mali-midgard";
reg = <0x0 0xffa30000 0x0 0x10000>;
interrupts = <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>;
interrupt-names = "JOB", "MMU", "GPU";
clocks = <&cru ACLK_GPU>;
clock-names = "clk_mali";
operating-points-v2 = <&gpu_opp_table>;
#cooling-cells = <2>; /* min followed by max */
power-domains = <&power RK3288_PD_GPU>;
status = "disabled";
upthreshold = <75>;
downdifferential = <10>;
gpu_power_model: power_model {
compatible = "arm,mali-simple-power-model";
static-coefficient = <411000>;
dynamic-coefficient = <733>;
ts = <32000 4700 (-80) 2>;
thermal-zone = "gpu-thermal";
};
};
gpu_opp_table: opp-table1 {
compatible = "operating-points-v2";
opp-100000000 {
opp-hz = /bits/ 64 <100000000>;
opp-microvolt = <950000>;
};
opp-200000000 {
opp-hz = /bits/ 64 <200000000>;
opp-microvolt = <950000>;
};
opp-300000000 {
opp-hz = /bits/ 64 <300000000>;
opp-microvolt = <1000000>;
};
opp-400000000 {
opp-hz = /bits/ 64 <400000000>;
opp-microvolt = <1100000>;
};
opp-500000000 {
opp-hz = /bits/ 64 <500000000>;
opp-microvolt = <1200000>;
};
};
noc: syscon@ffac0000 {
compatible = "rockchip,rk3288-noc", "syscon";
reg = <0x0 0xffac0000 0x0 0x2000>;
};
nocp_core: nocp-core@ffac0400 {
compatible = "rockchip,rk3288-nocp";
reg = <0x0 0xffac0400 0x0 0x400>;
};
nocp_gpu: nocp-gpu@ffac0800 {
compatible = "rockchip,rk3288-nocp";
reg = <0x0 0xffac0800 0x0 0x400>;
};
nocp_peri: nocp-peri@ffac0c00 {
compatible = "rockchip,rk3288-nocp";
reg = <0x0 0xffac0c00 0x0 0x400>;
};
nocp_vpu: nocp-vpu@ffac1000 {
compatible = "rockchip,rk3288-nocp";
reg = <0x0 0xffac1000 0x0 0x400>;
};
nocp_vio0: nocp-vio0@ffac1400 {
compatible = "rockchip,rk3288-nocp";
reg = <0x0 0xffac1400 0x0 0x400>;
};
nocp_vio1: nocp-vio1@ffac1800 {
compatible = "rockchip,rk3288-nocp";
reg = <0x0 0xffac1800 0x0 0x400>;
};
nocp_vio2: nocp-vio2@ffac1c00 {
compatible = "rockchip,rk3288-nocp";
reg = <0x0 0xffac1c00 0x0 0x400>;
};
efuse: efuse@ffb40000 {
compatible = "rockchip,rockchip-efuse";
reg = <0x0 0xffb40000 0x0 0x20>;
#address-cells = <1>;
#size-cells = <1>;
clocks = <&cru PCLK_EFUSE256>;
clock-names = "pclk_efuse";
special_function: special-function@5 {
reg = <0x5 0x1>;
bits = <4 4>;
};
process_version: process-version@6 {
reg = <0x6 0x1>;
bits = <0 4>;
};
efuse_id: id@7 {
reg = <0x7 0x10>;
};
cpu_leakage: cpu-leakage@17 {
reg = <0x17 0x1>;
};
performance_w: performance@1c {
reg = <0x1c 0x1>;
bits = <4 3>;
};
performance: performance@1d {
reg = <0x1d 0x1>;
bits = <4 3>;
};
};
gic: interrupt-controller@ffc01000 {
compatible = "arm,gic-400";
interrupt-controller;
#interrupt-cells = <3>;
#address-cells = <0>;
reg = <0x0 0xffc01000 0x0 0x1000>,
<0x0 0xffc02000 0x0 0x2000>,
<0x0 0xffc04000 0x0 0x2000>,
<0x0 0xffc06000 0x0 0x2000>;
interrupts = <GIC_PPI 9 0xf04>;
};
pinctrl: pinctrl {
compatible = "rockchip,rk3288-pinctrl";
rockchip,grf = <&grf>;
rockchip,pmu = <&pmu>;
#address-cells = <2>;
#size-cells = <2>;
ranges;
gpio0: gpio0@ff750000 {
compatible = "rockchip,gpio-bank";
reg = <0x0 0xff750000 0x0 0x100>;
interrupts = <GIC_SPI 81 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&cru PCLK_GPIO0>;
gpio-controller;
#gpio-cells = <2>;
interrupt-controller;
#interrupt-cells = <2>;
};
gpio1: gpio1@ff780000 {
compatible = "rockchip,gpio-bank";
reg = <0x0 0xff780000 0x0 0x100>;
interrupts = <GIC_SPI 82 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&cru PCLK_GPIO1>;
gpio-controller;
#gpio-cells = <2>;
interrupt-controller;
#interrupt-cells = <2>;
};
gpio2: gpio2@ff790000 {
compatible = "rockchip,gpio-bank";
reg = <0x0 0xff790000 0x0 0x100>;
interrupts = <GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&cru PCLK_GPIO2>;
gpio-controller;
#gpio-cells = <2>;
interrupt-controller;
#interrupt-cells = <2>;
};
gpio3: gpio3@ff7a0000 {
compatible = "rockchip,gpio-bank";
reg = <0x0 0xff7a0000 0x0 0x100>;
interrupts = <GIC_SPI 84 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&cru PCLK_GPIO3>;
gpio-controller;
#gpio-cells = <2>;
interrupt-controller;
#interrupt-cells = <2>;
};
gpio4: gpio4@ff7b0000 {
compatible = "rockchip,gpio-bank";
reg = <0x0 0xff7b0000 0x0 0x100>;
interrupts = <GIC_SPI 85 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&cru PCLK_GPIO4>;
gpio-controller;
#gpio-cells = <2>;
interrupt-controller;
#interrupt-cells = <2>;
};
gpio5: gpio5@ff7c0000 {
compatible = "rockchip,gpio-bank";
reg = <0x0 0xff7c0000 0x0 0x100>;
interrupts = <GIC_SPI 86 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&cru PCLK_GPIO5>;
gpio-controller;
#gpio-cells = <2>;
interrupt-controller;
#interrupt-cells = <2>;
};
gpio6: gpio6@ff7d0000 {
compatible = "rockchip,gpio-bank";
reg = <0x0 0xff7d0000 0x0 0x100>;
interrupts = <GIC_SPI 87 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&cru PCLK_GPIO6>;
gpio-controller;
#gpio-cells = <2>;
interrupt-controller;
#interrupt-cells = <2>;
};
gpio7: gpio7@ff7e0000 {
compatible = "rockchip,gpio-bank";
reg = <0x0 0xff7e0000 0x0 0x100>;
interrupts = <GIC_SPI 88 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&cru PCLK_GPIO7>;
gpio-controller;
#gpio-cells = <2>;
interrupt-controller;
#interrupt-cells = <2>;
};
gpio8: gpio8@ff7f0000 {
compatible = "rockchip,gpio-bank";
reg = <0x0 0xff7f0000 0x0 0x100>;
interrupts = <GIC_SPI 89 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&cru PCLK_GPIO8>;
gpio-controller;
#gpio-cells = <2>;
interrupt-controller;
#interrupt-cells = <2>;
};
hdmi {
hdmi_gpio: hdmi-gpio {
rockchip,pins = <7 19 RK_FUNC_GPIO
&pcfg_pull_none>,
<7 20 RK_FUNC_GPIO
&pcfg_pull_none>;
};
hdmi_ddc: hdmi-ddc {
rockchip,pins = <7 19 RK_FUNC_2 &pcfg_pull_none>,
<7 20 RK_FUNC_2 &pcfg_pull_none>;
};
};
pcfg_pull_up: pcfg-pull-up {
bias-pull-up;
};
pcfg_pull_down: pcfg-pull-down {
bias-pull-down;
};
pcfg_pull_none: pcfg-pull-none {
bias-disable;
};
pcfg_pull_none_12ma: pcfg-pull-none-12ma {
bias-disable;
drive-strength = <12>;
};
sleep {
global_pwroff: global-pwroff {
rockchip,pins = <0 0 RK_FUNC_1 &pcfg_pull_none>;
};
ddrio_pwroff: ddrio-pwroff {
rockchip,pins = <0 1 RK_FUNC_1 &pcfg_pull_none>;
};
ddr0_retention: ddr0-retention {
rockchip,pins = <0 2 RK_FUNC_1 &pcfg_pull_up>;
};
ddr1_retention: ddr1-retention {
rockchip,pins = <0 3 RK_FUNC_1 &pcfg_pull_up>;
};
};
edp {
edp_hpd: edp-hpd {
rockchip,pins = <7 11 RK_FUNC_2 &pcfg_pull_down>;
};
};
i2c0 {
i2c0_xfer: i2c0-xfer {
rockchip,pins = <0 15 RK_FUNC_1 &pcfg_pull_none>,
<0 16 RK_FUNC_1 &pcfg_pull_none>;
};
};
i2c1 {
i2c1_xfer: i2c1-xfer {
rockchip,pins = <8 4 RK_FUNC_1 &pcfg_pull_none>,
<8 5 RK_FUNC_1 &pcfg_pull_none>;
};
};
i2c2 {
i2c2_xfer: i2c2-xfer {
rockchip,pins = <6 9 RK_FUNC_1 &pcfg_pull_none>,
<6 10 RK_FUNC_1 &pcfg_pull_none>;
};
};
i2c3 {
i2c3_xfer: i2c3-xfer {
rockchip,pins = <2 16 RK_FUNC_1 &pcfg_pull_none>,
<2 17 RK_FUNC_1 &pcfg_pull_none>;
};
};
i2c4 {
i2c4_xfer: i2c4-xfer {
rockchip,pins = <7 17 RK_FUNC_1 &pcfg_pull_none>,
<7 18 RK_FUNC_1 &pcfg_pull_none>;
};
};
i2c5 {
i2c5_xfer: i2c5-xfer {
rockchip,pins = <7 19 RK_FUNC_1 &pcfg_pull_none>,
<7 20 RK_FUNC_1 &pcfg_pull_none>;
};
};
i2s0 {
i2s0_bus: i2s0-bus {
rockchip,pins = <6 0 RK_FUNC_1 &pcfg_pull_none>,
<6 1 RK_FUNC_1 &pcfg_pull_none>,
<6 2 RK_FUNC_1 &pcfg_pull_none>,
<6 3 RK_FUNC_1 &pcfg_pull_none>,
<6 4 RK_FUNC_1 &pcfg_pull_none>;
};
i2s0_mclk: i2s0-mclk {
rockchip,pins = <6 8 RK_FUNC_1 &pcfg_pull_none>;
};
};
lcdc {
lcdc_ctl: lcdc-ctl {
rockchip,pins = <1 24 RK_FUNC_1 &pcfg_pull_none>,
<1 25 RK_FUNC_1 &pcfg_pull_none>,
<1 26 RK_FUNC_1 &pcfg_pull_none>,
<1 27 RK_FUNC_1 &pcfg_pull_none>;
};
};
sdmmc {
sdmmc_clk: sdmmc-clk {
rockchip,pins = <6 20 RK_FUNC_1 &pcfg_pull_none>;
};
sdmmc_cmd: sdmmc-cmd {
rockchip,pins = <6 21 RK_FUNC_1 &pcfg_pull_up>;
};
sdmmc_cd: sdmmc-cd {
rockchip,pins = <6 22 RK_FUNC_1 &pcfg_pull_up>;
};
sdmmc_bus1: sdmmc-bus1 {
rockchip,pins = <6 16 RK_FUNC_1 &pcfg_pull_up>;
};
sdmmc_bus4: sdmmc-bus4 {
rockchip,pins = <6 16 RK_FUNC_1 &pcfg_pull_up>,
<6 17 RK_FUNC_1 &pcfg_pull_up>,
<6 18 RK_FUNC_1 &pcfg_pull_up>,
<6 19 RK_FUNC_1 &pcfg_pull_up>;
};
};
sdio0 {
sdio0_bus1: sdio0-bus1 {
rockchip,pins = <4 20 RK_FUNC_1 &pcfg_pull_up>;
};
sdio0_bus4: sdio0-bus4 {
rockchip,pins = <4 20 RK_FUNC_1 &pcfg_pull_up>,
<4 21 RK_FUNC_1 &pcfg_pull_up>,
<4 22 RK_FUNC_1 &pcfg_pull_up>,
<4 23 RK_FUNC_1 &pcfg_pull_up>;
};
sdio0_cmd: sdio0-cmd {
rockchip,pins = <4 24 RK_FUNC_1 &pcfg_pull_up>;
};
sdio0_clk: sdio0-clk {
rockchip,pins = <4 25 RK_FUNC_1 &pcfg_pull_none>;
};
sdio0_cd: sdio0-cd {
rockchip,pins = <4 26 RK_FUNC_1 &pcfg_pull_up>;
};
sdio0_wp: sdio0-wp {
rockchip,pins = <4 27 RK_FUNC_1 &pcfg_pull_up>;
};
sdio0_pwr: sdio0-pwr {
rockchip,pins = <4 28 RK_FUNC_1 &pcfg_pull_up>;
};
sdio0_bkpwr: sdio0-bkpwr {
rockchip,pins = <4 29 RK_FUNC_1 &pcfg_pull_up>;
};
sdio0_int: sdio0-int {
rockchip,pins = <4 30 RK_FUNC_1 &pcfg_pull_up>;
};
};
sdio1 {
sdio1_bus1: sdio1-bus1 {
rockchip,pins = <3 24 4 &pcfg_pull_up>;
};
sdio1_bus4: sdio1-bus4 {
rockchip,pins = <3 24 4 &pcfg_pull_up>,
<3 25 4 &pcfg_pull_up>,
<3 26 4 &pcfg_pull_up>,
<3 27 4 &pcfg_pull_up>;
};
sdio1_cd: sdio1-cd {
rockchip,pins = <3 28 4 &pcfg_pull_up>;
};
sdio1_wp: sdio1-wp {
rockchip,pins = <3 29 4 &pcfg_pull_up>;
};
sdio1_bkpwr: sdio1-bkpwr {
rockchip,pins = <3 30 4 &pcfg_pull_up>;
};
sdio1_int: sdio1-int {
rockchip,pins = <3 31 4 &pcfg_pull_up>;
};
sdio1_cmd: sdio1-cmd {
rockchip,pins = <4 6 4 &pcfg_pull_up>;
};
sdio1_clk: sdio1-clk {
rockchip,pins = <4 7 4 &pcfg_pull_none>;
};
sdio1_pwr: sdio1-pwr {
rockchip,pins = <4 9 4 &pcfg_pull_up>;
};
};
emmc {
emmc_clk: emmc-clk {
rockchip,pins = <3 18 RK_FUNC_2 &pcfg_pull_none>;
};
emmc_cmd: emmc-cmd {
rockchip,pins = <3 16 RK_FUNC_2 &pcfg_pull_up>;
};
emmc_pwr: emmc-pwr {
rockchip,pins = <3 9 RK_FUNC_2 &pcfg_pull_up>;
};
emmc_bus1: emmc-bus1 {
rockchip,pins = <3 0 RK_FUNC_2 &pcfg_pull_up>;
};
emmc_bus4: emmc-bus4 {
rockchip,pins = <3 0 RK_FUNC_2 &pcfg_pull_up>,
<3 1 RK_FUNC_2 &pcfg_pull_up>,
<3 2 RK_FUNC_2 &pcfg_pull_up>,
<3 3 RK_FUNC_2 &pcfg_pull_up>;
};
emmc_bus8: emmc-bus8 {
rockchip,pins = <3 0 RK_FUNC_2 &pcfg_pull_up>,
<3 1 RK_FUNC_2 &pcfg_pull_up>,
<3 2 RK_FUNC_2 &pcfg_pull_up>,
<3 3 RK_FUNC_2 &pcfg_pull_up>,
<3 4 RK_FUNC_2 &pcfg_pull_up>,
<3 5 RK_FUNC_2 &pcfg_pull_up>,
<3 6 RK_FUNC_2 &pcfg_pull_up>,
<3 7 RK_FUNC_2 &pcfg_pull_up>;
};
};
spi0 {
spi0_clk: spi0-clk {
rockchip,pins = <5 12 RK_FUNC_1 &pcfg_pull_up>;
};
spi0_cs0: spi0-cs0 {
rockchip,pins = <5 13 RK_FUNC_1 &pcfg_pull_up>;
};
spi0_tx: spi0-tx {
rockchip,pins = <5 14 RK_FUNC_1 &pcfg_pull_up>;
};
spi0_rx: spi0-rx {
rockchip,pins = <5 15 RK_FUNC_1 &pcfg_pull_up>;
};
spi0_cs1: spi0-cs1 {
rockchip,pins = <5 16 RK_FUNC_1 &pcfg_pull_up>;
};
};
spi1 {
spi1_clk: spi1-clk {
rockchip,pins = <7 12 RK_FUNC_2 &pcfg_pull_up>;
};
spi1_cs0: spi1-cs0 {
rockchip,pins = <7 13 RK_FUNC_2 &pcfg_pull_up>;
};
spi1_rx: spi1-rx {
rockchip,pins = <7 14 RK_FUNC_2 &pcfg_pull_up>;
};
spi1_tx: spi1-tx {
rockchip,pins = <7 15 RK_FUNC_2 &pcfg_pull_up>;
};
};
spi2 {
spi2_cs1: spi2-cs1 {
rockchip,pins = <8 3 RK_FUNC_1 &pcfg_pull_up>;
};
spi2_clk: spi2-clk {
rockchip,pins = <8 6 RK_FUNC_1 &pcfg_pull_up>;
};
spi2_cs0: spi2-cs0 {
rockchip,pins = <8 7 RK_FUNC_1 &pcfg_pull_up>;
};
spi2_rx: spi2-rx {
rockchip,pins = <8 8 RK_FUNC_1 &pcfg_pull_up>;
};
spi2_tx: spi2-tx {
rockchip,pins = <8 9 RK_FUNC_1 &pcfg_pull_up>;
};
};
uart0 {
uart0_xfer: uart0-xfer {
rockchip,pins = <4 16 RK_FUNC_1 &pcfg_pull_up>,
<4 17 RK_FUNC_1 &pcfg_pull_none>;
};
uart0_cts: uart0-cts {
rockchip,pins = <4 18 RK_FUNC_1 &pcfg_pull_up>;
};
uart0_rts: uart0-rts {
rockchip,pins = <4 19 RK_FUNC_1 &pcfg_pull_none>;
};
};
uart1 {
uart1_xfer: uart1-xfer {
rockchip,pins = <5 8 RK_FUNC_1 &pcfg_pull_up>,
<5 9 RK_FUNC_1 &pcfg_pull_none>;
};
uart1_cts: uart1-cts {
rockchip,pins = <5 10 RK_FUNC_1 &pcfg_pull_up>;
};
uart1_rts: uart1-rts {
rockchip,pins = <5 11 RK_FUNC_1 &pcfg_pull_none>;
};
};
uart2 {
uart2_xfer: uart2-xfer {
rockchip,pins = <7 22 RK_FUNC_1 &pcfg_pull_up>,
<7 23 RK_FUNC_1 &pcfg_pull_none>;
};
/* no rts / cts for uart2 */
};
uart3 {
uart3_xfer: uart3-xfer {
rockchip,pins = <7 7 RK_FUNC_1 &pcfg_pull_up>,
<7 8 RK_FUNC_1 &pcfg_pull_none>;
};
uart3_cts: uart3-cts {
rockchip,pins = <7 9 RK_FUNC_1 &pcfg_pull_up>;
};
uart3_rts: uart3-rts {
rockchip,pins = <7 10 RK_FUNC_1 &pcfg_pull_none>;
};
};
uart4 {
uart4_xfer: uart4-xfer {
rockchip,pins = <5 15 3 &pcfg_pull_up>,
<5 14 3 &pcfg_pull_none>;
};
uart4_cts: uart4-cts {
rockchip,pins = <5 12 3 &pcfg_pull_up>;
};
uart4_rts: uart4-rts {
rockchip,pins = <5 13 3 &pcfg_pull_none>;
};
};
tsadc {
otp_gpio: otp-gpio {
rockchip,pins = <0 10 RK_FUNC_GPIO &pcfg_pull_none>;
};
otp_out: otp-out {
rockchip,pins = <0 10 RK_FUNC_1 &pcfg_pull_none>;
};
};
pwm0 {
pwm0_pin: pwm0-pin {
rockchip,pins = <7 0 RK_FUNC_1 &pcfg_pull_none>;
};
pwm0_pin_pull_down: pwm0-pin-pull-down {
rockchip,pins = <7 0 RK_FUNC_1 &pcfg_pull_down>;
};
};
pwm1 {
pwm1_pin: pwm1-pin {
rockchip,pins = <7 1 RK_FUNC_1 &pcfg_pull_none>;
};
pwm1_pin_pull_down: pwm1-pin-pull-down {
rockchip,pins = <7 1 RK_FUNC_1 &pcfg_pull_down>;
};
};
pwm2 {
pwm2_pin: pwm2-pin {
rockchip,pins = <7 22 3 &pcfg_pull_none>;
};
pwm2_pin_pull_down: pwm2-pin-pull-down {
rockchip,pins = <7 22 3 &pcfg_pull_down>;
};
};
pwm3 {
pwm3_pin: pwm3-pin {
rockchip,pins = <7 23 3 &pcfg_pull_none>;
};
pwm3_pin_pull_down: pwm3-pin-pull-down {
rockchip,pins = <7 23 3 &pcfg_pull_down>;
};
};
gmac {
rgmii_pins: rgmii-pins {
rockchip,pins = <3 30 3 &pcfg_pull_none>,
<3 31 3 &pcfg_pull_none>,
<3 26 3 &pcfg_pull_none>,
<3 27 3 &pcfg_pull_none>,
<3 28 3 &pcfg_pull_none_12ma>,
<3 29 3 &pcfg_pull_none_12ma>,
<3 24 3 &pcfg_pull_none_12ma>,
<3 25 3 &pcfg_pull_none_12ma>,
<4 0 3 &pcfg_pull_none>,
<4 5 3 &pcfg_pull_none>,
<4 6 3 &pcfg_pull_none>,
<4 9 3 &pcfg_pull_none_12ma>,
<4 4 3 &pcfg_pull_none_12ma>,
<4 1 3 &pcfg_pull_none>,
<4 3 3 &pcfg_pull_none>;
};
rmii_pins: rmii-pins {
rockchip,pins = <3 30 3 &pcfg_pull_none>,
<3 31 3 &pcfg_pull_none>,
<3 28 3 &pcfg_pull_none>,
<3 29 3 &pcfg_pull_none>,
<4 0 3 &pcfg_pull_none>,
<4 5 3 &pcfg_pull_none>,
<4 4 3 &pcfg_pull_none>,
<4 1 3 &pcfg_pull_none>,
<4 2 3 &pcfg_pull_none>,
<4 3 3 &pcfg_pull_none>;
};
};
spdif {
spdif_tx: spdif-tx {
rockchip,pins = <RK_GPIO6 11 RK_FUNC_1 &pcfg_pull_none>;
};
};
cif {
cif_dvp_d2d9: cif-dvp-d2d9 {
rockchip,pins = <2 0 RK_FUNC_1 &pcfg_pull_none>,
<2 1 RK_FUNC_1 &pcfg_pull_none>,
<2 2 RK_FUNC_1 &pcfg_pull_none>,
<2 3 RK_FUNC_1 &pcfg_pull_none>,
<2 4 RK_FUNC_1 &pcfg_pull_none>,
<2 5 RK_FUNC_1 &pcfg_pull_none>,
<2 6 RK_FUNC_1 &pcfg_pull_none>,
<2 7 RK_FUNC_1 &pcfg_pull_none>,
<2 8 RK_FUNC_1 &pcfg_pull_none>,
<2 9 RK_FUNC_1 &pcfg_pull_none>,
<2 11 RK_FUNC_1 &pcfg_pull_none>;
};
};
isp_pin {
isp_mipi: isp-mipi {
rockchip,pins =
/* cif_clkout */
<2 11 RK_FUNC_1 &pcfg_pull_none>;
};
isp_dvp_d2d9: isp-d2d9 {
rockchip,pins =
/* cif_data2 ... cif_data9 */
<2 0 RK_FUNC_1 &pcfg_pull_none>,
<2 1 RK_FUNC_1 &pcfg_pull_none>,
<2 2 RK_FUNC_1 &pcfg_pull_none>,
<2 3 RK_FUNC_1 &pcfg_pull_none>,
<2 4 RK_FUNC_1 &pcfg_pull_none>,
<2 5 RK_FUNC_1 &pcfg_pull_none>,
<2 6 RK_FUNC_1 &pcfg_pull_none>,
<2 7 RK_FUNC_1 &pcfg_pull_none>,
/* cif_sync, cif_href */
<2 8 RK_FUNC_1 &pcfg_pull_none>,
<2 9 RK_FUNC_1 &pcfg_pull_none>,
/* cif_clkin, cif_clkout */
<2 10 RK_FUNC_1 &pcfg_pull_none>,
<2 11 RK_FUNC_1 &pcfg_pull_none>;
};
isp_dvp_d0d1: isp-d0d1 {
rockchip,pins =
/* cif_data0, cif_data1 */
<2 12 RK_FUNC_1 &pcfg_pull_none>,
<2 13 RK_FUNC_1 &pcfg_pull_none>;
};
isp_dvp_d10d11: isp-d10d11 {
rockchip,pins =
/* cif_data10, cif_data11 */
<2 14 RK_FUNC_1 &pcfg_pull_none>,
<2 15 RK_FUNC_1 &pcfg_pull_none>;
};
isp_dvp_d0d7: isp-d0d7 {
rockchip,pins =
/* cif_data0 ... cif_data7 */
<2 12 RK_FUNC_1 &pcfg_pull_none>,
<2 13 RK_FUNC_1 &pcfg_pull_none>,
<2 0 RK_FUNC_1 &pcfg_pull_none>,
<2 1 RK_FUNC_1 &pcfg_pull_none>,
<2 2 RK_FUNC_1 &pcfg_pull_none>,
<2 3 RK_FUNC_1 &pcfg_pull_none>,
<2 4 RK_FUNC_1 &pcfg_pull_none>,
<2 5 RK_FUNC_1 &pcfg_pull_none>;
};
isp_shutter: isp-shutter {
rockchip,pins =
/* SHUTTEREN, SHUTTERTRIG */
<7 12 RK_FUNC_2 &pcfg_pull_none>,
<7 15 RK_FUNC_2 &pcfg_pull_none>;
};
isp_flash_trigger: isp-flash-trigger {
rockchip,pins =
/* ISP_FLASHTRIGOU */
<7 13 RK_FUNC_2 &pcfg_pull_none>;
};
isp_prelight: isp-prelight {
rockchip,pins =
/* ISP_PRELIGHTTRIG */
<7 14 RK_FUNC_2 &pcfg_pull_none>;
};
isp_flash_trigger_as_gpio: isp-flash-trigger-as-gpio {
rockchip,pins =
/* ISP_FLASHTRIGOU */
<7 13 RK_FUNC_2 &pcfg_pull_none>;
};
};
};
rockchip_suspend: rockchip-suspend {
compatible = "rockchip,pm-rk3288";
status = "disabled";
rockchip,sleep-mode-config = <
(0
|RKPM_CTR_PWR_DMNS
|RKPM_CTR_GTCLKS
|RKPM_CTR_PLLS
|RKPM_CTR_ARMOFF_LPMD
|RKPM_CTR_SYSCLK_OSC_DIS
)
>;
rockchip,wakeup-config = <
(0
| RKPM_GPIO_WKUP_EN
)
>;
rockchip,pwm-regulator-config = <
(0
| PWM2_REGULATOR_EN
)
>;
};
};